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"A Low Power Reprogrammable Parallel Processing VLSI Architecture for ..."

Sabyasachi Mondal, Arijit De, P. K. Biswas (2005)

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DOI: 10.1109/ICVD.2005.17

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/vlsid/MondalDB05
Sabyasachi Mondal, Arijit De, P. K. Biswas:
A Low Power Reprogrammable Parallel Processing VLSI Architecture for Computation of B-Spline Based Medical Image Processing System for Fast Characterization of Tiny Objects Suspended in Cellular Fluid. VLSI Design 2005: 147-152

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