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ORCIDM. S. Bhat 0001
Person information
- affiliation: National Institute of Technology Karnataka, Surathkal, India
- affiliation (PhD 2007): Indian Institute of Science, Bangalore, India
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2020 – today
- 2024
[j15]Ramachandra Gambheer
, M. S. Bhat:
Optimized Compressed Sensing for IoT: Advanced Algorithms for Efficient Sparse Signal Reconstruction in Edge Devices. IEEE Access 12: 63610-63617 (2024)- 2023
- [j14]Ramachandra Gambheer, M. S. Bhat:
CCD Sensor Based Cameras for Sustainable Streaming IoT Applications With Compressed Sensing. IEEE Access 11: 67882-67892 (2023) - 2021
- [j13]Sreenivasulu Polineni, S. Rekha, M. S. Bhat:
A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications. IET Circuits Devices Syst. 15(2): 141-155 (2021) - 2020
- [j12]Sreenivasulu Polineni, M. S. Bhat, S. Rekha:
A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique. Circuits Syst. Signal Process. 39(11): 5352-5370 (2020) - [j11]G. Hanumantha Rao, Sreenivasulu Polineni, S. Rekha, M. S. Bhat:
A 0.3-V, 2.4-nW, and 100-Hz fourth-order LPF for ECG signal processing. Int. J. Circuit Theory Appl. 48(11): 1853-1863 (2020)
2010 – 2019
- 2019
- [j10]Sreenivasulu Polineni, G. Hanumanta Rao, S. Rekha, M. S. Bhat:
A 0.3 V, 56 dB DR, 100 Hz fourth order low-pass filter for ECG acquisition system. Microelectron. J. 94 (2019) - [c16]Samarth Bonthala, Yashas Uppoor, Ashika Nayak, Sreenivasulu Polineni, M. S. Bhat:
Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology. ISED 2019: 1-6 - 2018
- [j9]Jagadish Dasarahalli Narasimaiah, Laxminidhi Tonse, Mujoor Sankaranarayana Bhat:
11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal-oxide-semiconductor. IET Circuits Devices Syst. 12(3): 249-255 (2018) - [j8]Jagadish Dasarahalli Narasimaiah, Mujoor Shankaranarayana Bhat:
14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS. IET Circuits Devices Syst. 12(6): 671-680 (2018) - [j7]E. S. Shajahan, M. S. Bhat:
Fabrication and characterisation of RF MEMS capacitive switches tuned for X and Ku bands. Int. J. Mechatronics Autom. 6(2/3): 143-149 (2018) - [c15]E. S. Shajahan, M. S. Bhat:
High Isolation Single Pole Four Throw RF MEMS Switches for X band. ISED 2018: 251-255 - 2017
- [j6]B. Jhnanesh Somayaji, M. S. Bhat:
Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform. J. Low Power Electron. 13(4): 669-677 (2017) - [c14]Baldeo Sharan Sharma, M. S. Bhat:
Design of high performance dual-gate nano-scale In0.55Ga0.45 as transistor with modified substrate geometry. UEMCON 2017: 271-277 - 2016
- [c13]B. Jhnanesh Somayaji, M. S. Bhat:
Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications. ISED 2016: 72-76 - [c12]Suraj Hebbar, Vinay Kumar, M. S. Bhat, Navakanta Bhat:
Smart handheld platform for electrochemical bio sensors. VDAT 2016: 1-2 - 2015
- [j5]D. N. Jagadish, M. S. Bhat:
Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter. J. Low Power Electron. 11(3): 436-443 (2015) - 2014
- [j4]A. A. Bini, M. S. Bhat:
Despeckling low SNR, low contrast ultrasound images via anisotropic level set diffusion. Multidimens. Syst. Signal Process. 25(1): 41-65 (2014) - [j3]A. A. Bini, M. S. Bhat:
A nonlinear level set model for image deblurring and denoising. Vis. Comput. 30(3): 311-325 (2014) - [c11]Sadeque Reza Khan, Rajsekhar Kr. Nath, M. S. Bhat:
GSM and GUI Based Remote Data Logging System. ISED 2014: 29-32 - [c10]E. S. Shajahan, M. S. Bhat, B. Chenna Reddy:
Inductive Tuned High Isolation RF MEMS Capacitive Shunt Switches. ISED 2014: 33-37 - [c9]D. N. Jagadish, M. S. Bhat:
Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC. ISED 2014: 54-57 - [c8]D. N. Jagadish, M. S. Bhat:
A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications. ISED 2014: 58-62 - [c7]B. Chenna Reddy, E. S. Shajahan, M. S. Bhat:
Design of a triple band-notched circular monopole antenna for UWB applications. WOCN 2014: 1-5 - 2013
- [c6]R. Lagisetty, N. K. Philip, R. Padhi, M. S. Bhat:
Object detection and obstacle avoidance for mobile robot using stereo camera. CCA 2013: 605-610 - 2012
- [j2]K. Soorya Krishna, M. S. Bhat:
Minimization of Via-Induced Signal Reflection in On-Chip High Speed Interconnect Lines. Circuits Syst. Signal Process. 31(2): 689-702 (2012)
2000 – 2009
- 2009
- [j1]G. Rajashekar, M. S. Bhat:
Design of resolution adaptive TIQ flash ADC using AMS 0.35 µm technology. Int. J. Inf. Commun. Technol. 2(1/2): 19-30 (2009) - 2006
- [c5]M. S. Bhat, S. Rekha, H. S. Jamadagni:
Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits. VLSI Design 2006: 51-56 - 2005
- [c4]M. S. Bhat, H. S. Jamadagni:
Static power minimization in current-mode circuits. ASP-DAC 2005: 1220-1223 - [c3]M. S. Bhat, S. Rekha, H. S. Jamadagni:
An Extrinsic Method for the Synthesis of Analog Functions using Non-Linear Current-Mode Circuits. IICAI 2005: 209-220 - [c2]M. S. Bhat, S. Rekha, H. S. Jamadagni:
An Extrinsic Method of Evolutionary Synthesis of Multiple-Valued Arithmetic Functions using Genetic Algorithms. IICAI 2005: 221-231 - [c1]M. S. Bhat, H. S. Jamadagni:
Power Optimization in Current Mode Circuits. VLSI Design 2005: 175-180
Coauthor Index
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last updated on 2024-05-19 02:40 CEST by the dblp team
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