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Arindrajit Ghosh
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2020 – today
- 2020
- [j2]Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee:
Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology. Integr. 70: 126-137 (2020)
2010 – 2019
- 2018
- [j1]Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee:
Contention free delayed keeper for high density large signal sensing memory compiler. Integr. 62: 24-33 (2018)
2000 – 2009
- 2006
- [c3]Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee:
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. APCCAS 2006: 1-4 - 2005
- [c2]Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee:
A 160MSPS 8-Bit Pipeline Based ADC. VLSI Design 2005: 313-318 - [c1]Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey:
A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. VLSI Design 2005: 319-322
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last updated on 2024-04-24 23:06 CEST by the dblp team
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