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ORCIDRubin A. Parekhji
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2020 – today
- 2024
[c57]Tolga Aksoy, Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev:
Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling. ETS 2024: 1-6- [i1]Ayush Arunachalam, Ian Kintz, Suvadeep Banerjee, Arnab Raha, Xiankun Jin, Fei Su, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Suriyaprakash Natarajan, Kanad Basu:
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. CoRR abs/2404.01632 (2024) - 2022
- [c56]Rubin A. Parekhji:
Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI Systems. VTS 2022: 1 - 2021
- [c55]V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur:
Exploiting Application Tolerance for Functional Safety. ITC 2021: 399-408
2010 – 2019
- 2019
- [j10]Kanad Basu, Mingsong Chen, Rubin A. Parekhji:
Guest Editorial. J. Electron. Test. 35(5): 579-580 (2019) - [c54]V. Prasanth
, Rubin A. Parekhji, Bharadwaj Amrutur:
Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis. VLSID 2019: 293-298 - 2018
- [c53]Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji:
Towards Single Pin Scan for Extremely Low Pin Count Test. VLSID 2018: 97-102 - 2017
- [c52]Nimit Jain, Nitin Agarwal, Rajavelu Thinakaran, Rubin A. Parekhji:
Low cost dynamic error detection in linearity testing of SAR ADCs. ITC 2017: 1-8 - [c51]V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur:
Safety analysis for integrated circuits in the context of hybrid systems. ITC 2017: 1-10 - [c50]Rubin A. Parekhji, Srinivas Modekurty:
Innovative practices session 2C: "How is industry simplifying analog test". VTS 2017: 1 - [c49]Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji:
An optimised SDD ATPG and SDQL computation method across different pattern sets. VTS 2017: 1-6 - 2016
- [c48]Pankaj Bongale, Vinothkumar Sundaresan, Partha Ghosh, Rubin A. Parekhji:
A novel technique for interdependent trim code optimization. VTS 2016: 1-6 - 2015
- [j9]Rubin A. Parekhji, Kenneth Butler, Gordon W. Roberts:
Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs. IEEE Des. Test 32(1): 6-8 (2015) - [j8]Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Time-Division Multiplexing for Testing DVFS-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 668-681 (2015) - [c47]V. Prasanth, Rubin A. Parekhji, Bharadwaj S. Amrutur:
Improved Methods for Accurate Safety Analysis of Real-Life Systems. ATS 2015: 175-180 - [c46]Osman Emir Erol, Sule Ozev, Chandra K. H. Suresh, Rubin A. Parekhji, Lakshmanan Balasubramanian:
On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC. DATE 2015: 1559-1562 - [c45]V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji:
New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. VLSID 2015: 363-368 - 2014
- [c44]Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain:
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. DATE 2014: 1-6 - [c43]Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji:
Systematic approach for trim test time optimization: Case study on a multi-core RF SOC. ITC 2014: 1-9 - 2013
- [c42]Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji:
Towards adaptive test of multi-core RF SoCs. DATE 2013: 743-748 - 2012
- [j7]Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1754-1766 (2012) - [c41]Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. ETS 2012: 1-6 - [c40]V. Prasanth, Virendra Singh, Rubin A. Parekhji:
Derating based hardware optimizations in soft error tolerant designs. VTS 2012: 282-287 - 2011
- [j6]Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electron. 7(4): 502-515 (2011) - [c39]Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. Asian Test Symposium 2011: 33-39 - [c38]V. Prasanth, Virendra Singh, Rubin A. Parekhji:
Reduced overhead soft error mitigation using error control coding techniques. IOLTS 2011: 163-168 - [c37]Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji:
DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. ITC 2011: 1-10 - [c36]Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
Multi-CoDec Configurations for Low Power and High Quality Scan Test. VLSI Design 2011: 370-375 - [c35]Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal:
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. VTS 2011: 285-290 - 2010
- [j5]M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji:
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms. J. Electron. Test. 26(3): 323-335 (2010) - [c34]V. Prasanth, Virendra Singh, Rubin A. Parekhji:
Robust detection of soft errors using delayed capture methodology. IOLTS 2010: 277-282 - [c33]Rubin A. Parekhji:
Innovative practices session 1C: Innovative practices in RF test. VTS 2010: 39 - [c32]Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji:
Test time reduction using parallel RF test techniques. VTS 2010: 40 - [c31]Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji:
A generic low power scan chain wrapper for designs using scan compression. VTS 2010: 135-140
2000 – 2009
- 2009
- [c30]Hongxia Fang, Krishnendu Chakrabarty, Rubin A. Parekhji:
Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. Asian Test Symposium 2009: 331-336 - [c29]Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji:
Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. IOLTS 2009: 237-242 - 2008
- [j4]Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena:
Low Power Test for Nanometer System-on-Chips (SoCs). J. Low Power Electron. 4(1): 81-100 (2008) - [c28]Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams:
Evaluation of Entropy Driven Compression Bounds on Industrial Designs. ATS 2008: 13-18 - [c27]Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill:
Power Analysis and Reduction Techniques for Transition Fault Testing. ATS 2008: 403-408 - [c26]M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji:
False Error Study of On-line Soft Error Detection Mechanisms. IOLTS 2008: 53-58 - [c25]Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji:
DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. ITC 2008: 1-10 - [c24]Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan:
A systematic approach to synthesis of verification test-suites for modular SoC designs. SoCC 2008: 91-96 - [c23]Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji:
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. VTS 2008: 53-58 - 2007
- [c22]Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic. ICCAD 2007: 526-529 - [c21]Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji:
Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. VLSI Design 2007: 339-344 - [c20]Subir K. Roy, Rubin A. Parekhji:
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. VLSI Design 2007: 364-372 - [c19]Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji:
Modified Stability Checking for On-line Error Detection. VLSI Design 2007: 787-792 - 2006
- [c18]Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar:
On-chip Test and Repair of Memories for Static and Dynamic Faults. ITC 2006: 1-10 - [c17]Rubin A. Parekhji:
Session Abstract. VTS 2006: 86-87 - 2005
- [c16]Sameer Goel, Rubin A. Parekhji:
Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. Asian Test Symposium 2005: 330-336 - [c15]Rubin A. Parekhji:
DFT for Low Cost SOC Test. Asian Test Symposium 2005: 451 - 2004
- [j3]Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken:
ITC 2003 panels: Part 1. IEEE Des. Test Comput. 21(2): 160-163 (2004) - [c14]Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji:
CESC: a visual formalism for specification and verification of SoCs. ACM Great Lakes Symposium on VLSI 2004: 354-357 - [c13]K. Nikila, Rubin A. Parekhji:
DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. ITC 2004: 773-782 - [c12]Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar:
Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. VLSI Design 2004: 753-756 - 2003
- [c11]Rubin A. Parekhji:
Panel Synopsis - How (In)Adequate is One Time Testing? ITC 2003: 1279 - [c10]Rubin A. Parekhji:
Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. VLSI Design 2003: 17 - 2002
- [c9]Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji:
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. ASP-DAC/VLSI Design 2002: 781-788 - 2000
- [c8]Ameet Bagwe, Rubin A. Parekhji:
Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. Asian Test Symposium 2000: 260- - [c7]Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji:
A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. ITC 2000: 417-425 - [c6]Rubin A. Parekhji:
Test Techniques and Trade-offs for Embedded Cores and Systems. VLSI Design 2000: 5
1990 – 1999
- 1996
- [j2]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
Monitoring machine based synthesis technique for concurrent error detection in finite state machines. J. Electron. Test. 8(2): 179-201 (1996) - [c5]Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit:
E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. Asian Test Symposium 1996: 34-41 - 1995
- [j1]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
Concurrent Error Detection Using Monitoring Machines. IEEE Des. Test Comput. 12(3): 24-32 (1995) - [c4]B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh:
A new methodology for the design of low-cost fail safe circuits and networks. VLSI Design 1995: 355-358 - 1993
- [c3]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. VLSI Design 1993: 15-20 - 1991
- [c2]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
A Methodology for Designing Optimal Self-Checking Sequential Circuits. ITC 1991: 283-291
1980 – 1989
- 1989
- [c1]Rubin A. Parekhji, N. K. Nanda:
Design methodology and microdiagnostics development for a self-checking microprocessor. MICRO 1989: 70-82
Coauthor Index
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