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"34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for ..."

Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu (2004)

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DOI: 10.1109/TEST.2004.1387399

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu:
34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. ITC 2004: 1255-1262

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