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"High-speed multiplier design using multi-input counter and compressor ..."

Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr. (1991)

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DOI: 10.1109/ARITH.1991.145532

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr.:
High-speed multiplier design using multi-input counter and compressor circuits. IEEE Symposium on Computer Arithmetic 1991: 43-50

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