default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDThe Journal of VLSI Signal Processing, Volume 4
Volume 4, Number 1, February 1992
- Miguel Valero-García, Juan J. Navarro, José María Llabería
, Mateo Valero, Tomás Lang:
A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. 7-25 - Philippe Clauss, Catherine Mongenet, Guy-René Perrin:
Calculus of space-optimal mappings of systolic algorithms on processor arrays. 27-36 - G. Jack Lipovski:
A four megabit Dynamic Systolic Associative Memory chip. 37-51 - C. F. T. Tang, K. J. Ray Liu, Shih-Fu Hsieh, Kung Yao:
VLSI algorithms and architectures for complex householder transformation with applications to array processing. 53-68 - Jean-Marc Delosme:
Bit-level systolic algorithms for real symmetric and Hermitian eigenvalue problems. 69-88 - Christian Lengauer, Jingling Xue:
A systolic array for pyramidal algorithms. 89
Volume 4, Numbers 2-3, May 1992
- Kung Yao:
Introduction. 95-96 - Xiaoxiong Zhong, Sanjay V. Rajopadhye:
Quasi-Linear allocation functions for efficient array design. 97-110 - K. Wojtek Przytula, Viktor K. Prasanna, Wei-Ming Lin:
Parallel implementation of neural networks. 111-123 - Yin-Tsung Hwang, Yu Hen Hu:
MSSM - A design aid for multi-stage systolic mapping. 125-145 - Magdy A. Bayoumi, Padma Rao, Bassem A. Alhalabi:
VLSI parallel architecture for Kalman filterAn algorithm specific approach. 147-163 - Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa:
A radix-8 wafer scale FFT processor. 165-176 - Hosahalli R. Srinivas, Keshab K. Parhi:
High-speed VLSI arithmetic processor architectures using hybrid number representation. 177-198 - Paul M. Chau, Scott R. Powell:
Power dissipation of VLSI array processing systems. 199-212 - Linda Kwai-Lin Lau, Rajeev Jain, Henry Samueli, Henry T. Nicholas III, Etan G. Cohen:
DDFSGEN. 213-226 - M. Yan, John V. McCanny:
Systolic inner product arrays with automatic word rounding. 227-242 - Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Jerry J. Cupal:
Initializing RAM-based logarithmic processors. 243-252
Volume 4, Number 4, November 1992
- Michaël F. X. B. van Swaaij, Francky Catthoor, Hugo De Man:
Nonlinear transformations for high level regular array ASIC synthesis. 259-268 - Rajinder Jit Singh, John V. McCanny:
High performance VLSI architecture for Wave Digital Filtering. 269-278 - Xiaoxiong Zhong, Sanjay V. Rajopadhye, Ivan Wong:
Systematic generation of linear allocation functions in systolic array design. 279-293 - Anna Antola, Roberto M. Negrini, Mariagiovanna Sami, Nello Scarabottolo:
Fault tolerance in FFT arrays: Time redundancy approaches. 295-316 - Jung Hwan Kim, Phill-Kyu Rhee:
A resource-efficient reconfiguration algorithm of VLSI 2-D processor arrays. 317-330 - Edwin Hsing-Mean Sha, Kenneth Steiglitz:
Error detection in arrays via dependency graphs. 331-342 - Tatyana D. Roziner, Mark G. Karpovsky:
Multidimensional fourier transforms by systolic architectures. 343-354 - K. S. Arun, D. R. Wagner:
High-speed digital filtering: Structures and finite wordlength effects. 355-370 - Zhi-Jian (Alex) Mou:
A study of VLSI symmetric FIR filter structures. 371-377
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-07-10 20:41 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
