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ORCIDWojciech Maly
Wojciech P. Maly
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- affiliation: Carnegie Mellon University, Pittsburgh, USA
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2010 – 2019
- 2015
[j26]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 869-878 (2015)- 2014
- [j25]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 495-506 (2014) - 2013
- [c76]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD 2013: 130-136 - 2012
- [c75]Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED 2012: 384-390 - 2011
- [j24]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 229-241 (2011) - [c74]Wojciech Maly:
Vertical slit transistor based integrated circuits (veSTICs): feasibility study. ISPD 2011: 147-148 - 2010
- [j23]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 197-210 (2010) - [c73]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Performance study of VeSFET-based, high-density regular circuits. ISPD 2010: 161-168 - [c72]Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly:
Evaluating yield and testing impact of sub-wavelength lithography. VTS 2010: 200-205
2000 – 2009
- 2009
- [c71]Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz
, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel:
Adder Circuits with Transistors using Independently Controlled Gates. ISCAS 2009: 449-452 - [c70]Wojciech Maly:
Vertical slit transistor based integrated circuits (VeSTICs) paradigm. ISPD 2009: 63-64 - [c69]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Transistor-level layout of high-density regular circuits. ISPD 2009: 83-90 - 2008
- [c68]Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey:
More Moore: foolish, feasible, or fundamentally different? ICCAD 2008: 9 - [c67]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz:
Is there always performance overhead for regular fabric? ICCD 2008: 557-562 - 2007
- [c66]Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska:
OPC-Free and Minimally Irregular IC Design Style. DAC 2007: 954-957 - 2006
- [j22]Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer:
Extracting Defect Density and Size Distributions from Product ICs. IEEE Des. Test Comput. 23(5): 390-400 (2006) - [c65]Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton:
Extraction of defect density and size distributions from wafer sort test results. DATE 2006: 913-918 - 2005
- [j21]Yangdong Deng, Wojciech P. Maly:
2.5-dimensional VLSI system integration. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 668-677 (2005) - 2004
- [c64]Yangdong Steve Deng, Wojciech Maly:
2.5D system integration: a design driven system implementation schema. ASP-DAC 2004: 450-455 - [c63]Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary:
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC 2004: 508-517 - 2003
- [c62]Yangdong Deng, Wojciech Maly:
Physical Design of the "2.5D" Stacked System. ICCD 2003: 211-217 - [c61]Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton:
Progressive Bridge Identification. ITC 2003: 309-318 - [c60]Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey:
Deformations of IC Structure in Test and Yield Learning. ITC 2003: 856-865 - 2002
- [j20]Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly:
Modeling the Economics of Testing: A DFT Perspective. IEEE Des. Test Comput. 19(1): 29-41 (2002) - [c59]Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels:
Fault Tuples in Diagnosis of Deep-Submicron Circuits. ITC 2002: 233-241 - 2001
- [j19]Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE 89(3): 341-365 (2001) - [c58]Wojciech Maly:
IC Design in High-Cost Nanometer-Technologies Era. DAC 2001: 9-14 - [c57]Yangdong Deng, Wojciech Maly:
Interconnect characteristics of 2.5-D system integration scheme. ISPD 2001: 171-175 - [c56]Wojciech Maly:
Quality of Design from an IC Manufacturing Perspective. ISQED 2001: 235-236 - [c55]John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC 2001: 258-267 - [c54]John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare:
Enabling Embedded Memory Diagnosis via Test Response Compression. VTS 2001: 292-298 - 2000
- [c53]Peng Li, Pranab K. Nag, Wojciech Maly:
Cost based tradeoff analysis of standard cell designs. SLIP 2000: 129-135
1990 – 1999
- 1999
- [j18]Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly:
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 151-162 (1999) - [j17]Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas:
An algorithm for determining repetitive patterns in very large IC layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 494-501 (1999) - 1998
- [c52]Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare:
Design-Manufacturing Interface: Part I - Vision. DATE 1998: 550-556 - [c51]Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon:
Design-Manufacturing Interface: Part II - Applications. DATE 1998: 557-562 - [c50]Hans T. Heineken, Wojciech Maly:
Performance - Manufacturability Tradeoffs in IC Design. DATE 1998: 563-567 - [c49]Wojciech Maly:
Moore's law and physical design of ICs. ISPD 1998: 36 - [c48]Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas:
A pattern matching algorithm for verification and analysis of very large IC layouts. ISPD 1998: 129-134 - [c47]Anne E. Gattiker, Wojciech Maly:
Toward understanding "Iddq-only" fails. ITC 1998: 174-183 - [c46]Anne E. Gattiker, Wojciech Maly:
Current signatures: application [to CMOS]. ITC 1998: 1168-1177 - 1997
- [j16]Anne E. Gattiker, Wojciech Maly:
Smart Substrate MCMs. J. Electron. Test. 10(1-2): 39-53 (1997) - [j15]Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly:
Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 528-543 (1997) - [c45]Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface. DAC 1997: 321-326 - [c44]Witold A. Pleskacz, Wojciech Maly:
Improved Yield Model for Submicron Domain. DFT 1997: 2-10 - [c43]Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken:
Detection of Yield Trends. DFT 1997: 62-68 - [c42]Anne E. Gattiker, Wojciech Maly:
Current Signatures: Application. ITC 1997: 156-165 - [c41]Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly:
To DFT or Not to DFT? ITC 1997: 557-566 - [c40]Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly:
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. ITC 1997: 1037-1038 - 1996
- [j14]Wojciech Maly:
The future of IC design, testing, and manufacturing. IEEE Des. Test Comput. 13(4): 8, 89-91 (1996) - [j13]Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski:
A complexity analysis of sequential ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1409-1423 (1996) - [c39]Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly:
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC 1996: 578-583 - [c38]Charles H. Ouyang, Witold A. Pleskacz, Wojciech Maly:
Extraction of critical areas for opens in large VLSI circuits. DFT 1996: 21-29 - [c37]Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker:
Fatal Fault Probability Prediction for Array Based Designs. DFT 1996: 30-38 - [c36]Wojciech Maly, Charles H. Ouyang, Subhendra Ghosh, Sury Maturi:
Detection of an antenna effect in VLSI designs. DFT 1996: 86-95 - [c35]Hans T. Heineken, Wojciech Maly:
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. ICCAD 1996: 368-373 - [c34]Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag:
Design for manufacturability in submicron domain. ICCAD 1996: 690-697 - [c33]Thomas E. Marchok, Wojciech Maly:
Modeling the Difficulty of Sequential Automatic Test Pattern Generation. ICCD 1996: 261-271 - [c32]Wojciech Maly:
New and Not-So-New Test Challenges of the Next Decade. ITC 1996: 11 - [c31]Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792 - [c30]Anne E. Gattiker, Wojciech Maly:
Current signatures [VLSI circuit testing]. VTS 1996: 112-117 - [c29]R. L. Campbell, P. Kuekes, David Y. Lepejian, Wojciech P. Maly, Michael Nicolaidis, Alex Orailoglu:
Can Defect-Tolerant Chips Better Meet the Quality Challenge? VTS 1996: 362-363 - [c28]Jitendra Khare, Wojciech Maly, Nathan Tiday:
Fault characterization of standard cell libraries using inductive contamination. VTS 1996: 405-413 - 1995
- [j12]Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly:
Testability Implications of Performance-Driven Logic Synthesis. IEEE Des. Test Comput. 12(2): 32-39 (1995) - [c27]Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly:
On Test Set Preservation of Retimed Circuits. DAC 1995: 176-182 - [c26]Thomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski:
Complexity of sequential ATPG. ED&TC 1995: 252-261 - [c25]Igor Bubel, Wojciech Maly, Thomas Waas, Pranab K. Nag, Hans Hartmann, Doris Schmitt-Landsiedel, Susanne Griep:
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout. DFT 1995: 10-18 - [c24]Pranab K. Nag, Wojciech Maly:
Hierarchical extraction of critical area for shorts in very large ICs. DFT 1995: 19-27 - [c23]Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly:
Accurate yield estimation of circuits with redundancy. DFT 1995: 155-163 - [c22]Jitendra Khare, Wojciech Maly:
Inductive Contamination Analysis (ICA) with SRAM Application. ITC 1995: 552-560 - 1994
- [j11]Wojciech Maly, Derek Feltham, Anne E. Gattiker, Mark D. Hobaugh, Kenneth Backus, Michael E. Thomas:
Smart-Substrate Multichip-Module Systems. IEEE Des. Test Comput. 11(2): 64-73 (1994) - [c21]Wojciech Maly:
Cost of Silicon Viewed from VLSI Design Perspective. DAC 1994: 135-142 - [c20]Anne E. Gattiker, Wojciech Maly:
Feasibility Study of Smart Substrate Multichip Modules. ITC 1994: 41-49 - [c19]Wojciech Maly:
Integration of Design, Manufacturing and Testing. ITC 1994: 1017 - 1993
- [j10]Samir Naik, Frank Agricola, Wojciech Maly:
Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing. IEEE Des. Test Comput. 10(2): 13-23 (1993) - [c18]Samir B. Naik, Wojciech P. Maly:
Computer-aided failure analysis of VLSI circuits using IDDQ testing. VTS 1993: 106-108 - [c17]Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly:
Estimation of reject ratio in testing of combinatorial circuits. VTS 1993: 319-325 - 1992
- [j9]Wojciech Maly:
Prospects for WSI: A Manufacturing Perspective. Computer 25(4): 58-65 (1992) - [j8]Wojciech Maly, Marek J. Patyra:
Design of ICs applying built-in current testing. J. Electron. Test. 3(4): 397-406 (1992) - [c16]Derek Feltham, Jitendra Khare, Wojciech Maly:
Design for testability view on placement and routing. EURO-DAC 1992: 382-387 - 1991
- [c15]Wojciech Maly:
What is Design for Manufacturability (DFM)? (Panel Abstract). DAC 1991: 252 - [c14]Thomas M. Storey, Wojciech Maly, John Andrews, Myron Miske:
Stuck Fault and Current Testing Comparison Using CMOS Chip Test. ITC 1991: 311-318 - [c13]Anne Meixner, Wojciech Maly:
Fault Modeling for the Testing of Mixed Integrated Circuits. ITC 1991: 564-572 - [c12]Wojciech Maly:
Improving the Quality of Test Education. ITC 1991: 1119 - 1990
- [j7]Phil Nigh, Wojciech Maly:
Test Generation for Current Testing (CMOS ICs). IEEE Des. Test Comput. 7(1): 26-38 (1990) - [j6]Wojciech Maly:
Computer-aided design for VLSI circuit manufacturability. Proc. IEEE 78(2): 356-392 (1990) - [c11]Wojciech Maly:
Current testing. ITC 1990: 257 - [c10]Thomas M. Storey, Wojciech Maly:
CMOS bridging fault detection. ITC 1990: 842-851 - [c9]Thomas M. Storey, Wojciech Maly:
CMOS Bridging Fault Detection. ITC 1990: 1123-1132
1980 – 1989
- 1989
- [c8]Phil Nigh, Wojciech Maly:
Layout-driven test generation. ICCAD 1989: 154-157 - [c7]Wojciech Maly, Samir B. Naik:
Process Monitoring Oriented IC Testing. ITC 1989: 527-532 - 1988
- [c6]Wojciech Maly, Phil Nigh:
Built-in current testing-feasibility study. ICCAD 1988: 340-343 - [c5]Wojciech Maly, Pranab K. Nag, Phil Nigh:
Testing oriented analysis of CMOS ICs with opens. ICCAD 1988: 344-347 - [c4]Derek Feltham, Phil Nigh, L. Richard Carley, Wojciech Maly:
Current sensing for built-in testing of CMOS circuits. ICCD 1988: 454-457 - 1987
- [c3]Wojciech Maly:
Realistic Fault Modeling for VLSI Testing. DAC 1987: 173-180 - 1986
- [j5]Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director:
VLSI Yield Prediction and Estimation: A Unified Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1): 114-130 (1986) - [c2]Wojciech Maly:
Optimal order of the VLSI IC testing sequence. DAC 1986: 560-566 - 1985
- [j4]John Paul Shen, Wojciech Maly, F. Joel Ferguson:
Inductive Fault Analysis of MOS Integrated Circuits. IEEE Des. Test 2(6): 13-26 (1985) - [j3]Wojciech Maly, Zygmunt Pizlo:
Tolerance Assignment for IC Selection Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(2): 156-162 (1985) - [j2]Wojciech Maly:
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 166-177 (1985) - 1984
- [c1]Wojciech Maly, F. Joel Ferguson, John Paul Shen:
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. ITC 1984: 390-399 - 1982
- [j1]Wojciech Maly, Andrzej J. Strojwas:
Statistical Simulation of the IC Manufacturing Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1(3): 120-131 (1982)
Coauthor Index
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