default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 1984: Philadelphia, PA, USA
- Proceedings International Test Conference 1984, Philadelphia, PA, USA, October 1984. IEEE Computer Society 1984
Session 1: Test Economics
- Mark A. Myers:
DeltaI vs. DeltaY : A Quantitative Analysis of the Trade-offs Between Higher Capital Investment and Higher Yield in PCB Testing. ITC 1984: 8-19 - Prab Varma, Anthony P. Ambler, Keith Baker:
An Analysis of the Economics of Self Test. ITC 1984: 20-30 - J. S. Pittman, William C. Bruce:
Test Logic Economic Considerations in a Commercial VLSI Chip Environment. ITC 1984: 31-39 - Gordon H. Bowers Jr., Bruce G. Pratt:
"Low Cost Testers" : Are They Really Low Cost ? ITC 1984: 40-51
Session 2: Update on Automatic Test Pattern Generation
- Joseph L. A. Hughes, Edward J. McCluskey:
An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets. ITC 1984: 52-58 - J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem:
Test Generation for FET Switching Circuits. ITC 1984: 59-62 - Brian J. Heard, Ramu N. Sheshadri, Ronald B. David, Arvid G. Sammuli:
Automatic Test Pattern Generation for Asynchronous Networks. ITC 1984: 63-69 - Harry H. Chen, Robert G. Mathews, John A. Newkirk:
Test Generation for MOS Circuits. ITC 1984: 70-79 - Erwin Trischler:
ATWIG, An Automatic Test Pattern Generator with Inherent Guidance. ITC 1984: 80-87 - Tohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka:
Logic Design Verification Using Automated Test Generation. ITC 1984: 88-95
Session 3: New Developments in Test System Accuracy
- Alexander Holland:
High Resolution, High Linearity Interpolating A/D Converter. ITC 1984: 96-104 - William B. Abbott IV:
Time Specification Conformance of VLSI Test Systems O5. ITC 1984: 105-112 - Y. Nishimura, Mitsuhiro Hamada, Y. Hayasaka:
A New Timing Calibration Method for High Speed Memory Test. ITC 1984: 113-117 - Anthony J. Burke:
Software Convergence of Test Program Parameters. ITC 1984: 118-122 - Tadaaki Satoh, Akira Takagi, Masami Kita, Katsuhiko Shirakawa, Shimpei Takeshita:
21-Bit Precision and High-Speed DC Measurement System. ITC 1984: 123-133
Session 4: Built-In Self Test Design and Analysis Techniques
- Dilip K. Bhavsar, Balakrishnan Krishnamurthy:
Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? ITC 1984: 134-139 - Yervant Zorian, Vinod K. Agarwal:
Higher Certainty of Error Coverage by Output Data Modification. ITC 1984: 140-147 - Zuhi Sun, Laung-Terng Wang:
Self-Testing of Embedded RAMs. ITC 1984: 148-156 - William H. McAnney, Paul H. Bardell, V. P. Gupta:
Random Testing for Stuck-At Storage Cells in an Embedded Memory. ITC 1984: 157-166 - Tom W. Williams:
Sufficient Testing In A Self-Testing Environment. ITC 1984: 167-173
Panel Session 5: Implications of Hardware Design Language
- Bulent I. Dervisoglu:
On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification. ITC 1984: 184-187
Session 6: Artificial Intelligence in VLSI Test Systems
- A. Jesse Wilkinson:
A Method for Test System Diagnostics Based on the Principles of Artificial Intelligence. ITC 1984: 188-195 - Robert Mullis:
An Expert System for VLSI Tester Diagnostics. ITC 1984: 196-199 - Gordon D. Robinson:
Artificial Intelligence and Testing. ITC 1984: 200-205
Session 7: Printed Circult Board Manufacturing Process and Test Data Management
- Brian C. Crosby:
Adapting CAE Design Information for In-Circuit Test Generation. ITC 1984: 206-211 - Graeme R. Kinsey:
Information and Material Flow Within a Production Test Cell. ITC 1984: 212-217
Session 8: Recent Developments in Computer Alded Testing
- Dharma P. Agrawal, Sami A. Al-Arian:
Comprehensive Fault Model and Testing of CMOS Circuits. ITC 1984: 218-223 - Leslie Turner Smith, Roy R. Rezac:
Methodology for and Results from the Use of a Hardware Logic Simulation Engine for Fault Simulation. ITC 1984: 224-228 - Arthur Babitz, Kurt Lender:
Using Simulation in the Design Process - A Case Study. ITC 1984: 229-236 - Yashwant K. Malaiya, Shoubao Yang:
The Coverage Problem for Random Testing. ITC 1984: 237-245 - Ramin Khorram:
Functional Test Pattern Generation for Integrated Circuits. ITC 1984: 246-249 - M. Melgara, M. Paolini, R. Roncella, S. Morpurgo:
CVT-FERT : Automatic Generator of Analytical Faults at Register Transfer Level from Electrical and Topological Descriptions. ITC 1984: 250-257
Session 9: Memory Test
- Frederick G. Hall, Robert G. Hillman, John M. Bednarczyk:
"Instant On" Semiconductor Memories: Reality or Myth. ITC 1984: 258-262 - E. Kurzweil, L. Jambut:
Access Time Evaluation of Fast Static MOS Memories. ITC 1984: 263-270 - Kozo Kinoshita, Kewal K. Saluja:
Built-in Testing of Memory Using On-chip Compact Testing Scheme. ITC 1984: 271-281 - Gene P. Bosse:
High Speed Redundancy Processor. ITC 1984: 282-286 - John R. Day:
A Fault-Driven, Comprehensive Redundancy Algorithm for Repair of Dynamic RAMs. ITC 1984: 287-293 - F. Pool, J. Hop, J. P. L. Lagerberg, C. Da Costa:
Testing a 317K bit High Speed Video Memory with a VSLI Test System. ITC 1984: 294-301
Session 10: Stimulus Generation and Application for Built-In-Self Test
- Paul H. Bardell, William H. McAnney:
Parallel Pseudorandom Sequences for Built-In Test. ITC 1984: 302-308 - Corot W. Starke:
Built-In Test for CMOS Circuits. ITC 1984: 309-314 - Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham:
Design of Test Pattern Generators for Built-In Test. ITC 1984: 315-319 - Syed Zahoor Hassan, Edward J. McCluskey:
Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis. ITC 1984: 320-326 - Charles R. Kime, H. H. Kwan, J. K. Lemke, Gerald B. Williams:
A Built-In Test Methodology for VLSI Data Paths. ITC 1984: 327-337 - Yacoub M. El-Ziq, Hamid H. Butt:
Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design. ITC 1984: 338-349
Session 11: Intergrated Circult Manufacturing Process and Test Data Management
- Dean Bandes:
Exploratory Data Analysis Makes Testing More Valuable for Semiconductor Manufacturing. ITC 1984: 350-358 - Kou Wada, Satoshi Tazawa, Katsutoshi Kubota:
A Flexible Database System and Its Application in VLSI Process Development. ITC 1984: 359-366 - Robert W. Atherton, Leonard Ekkelkamp, Chuck Schmitz:
Logic Device Characterization Using Computer-Aided Test and Analysis. ITC 1984: 367-383
Session 12: Physical Tralt Measurement on Components
- Sushil K. Malik, E. F. Chace:
MOS Gate Oxide Quality Control and Reliability Assessment by Voltage Ramping. ITC 1984: 384-389 - Wojciech Maly, F. Joel Ferguson, John Paul Shen:
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. ITC 1984: 390-399 - G. Siva Bushanam, Vance R. Harwood, Philip N. King, Roger D. Story:
Measuring Thermal Rises Due to Digital Device Overdriving. ITC 1984: 400-425
Session 13: Analog and Hybrid Testing
- E. A. Sloane:
Transfer Function Estimation Part I : Theoretical and Practical Considerations. ITC 1984: 426-439 - James F. Campbell Jr.:
Transfer Function Estimation Part II : Some Experimental Results. ITC 1984: 440-446 - Douglas K. Shirachi:
CODEC Testing Using Synchronized Analog and Digital Signals. ITC 1984: 447-454 - Terence Lee:
In-Circuit Analog Component Testing at High Frequencies. ITC 1984: 455-461
Session 14: New Directions for VLSI Test Systems
- Robert S. Broughton, Michael G. Brashler:
The Future is Now: Extending CAE into Test of Custom VLSI. ITC 1984: 462-465 - Donald L. Wheater:
IBM's Cost Performance Array Tester Architecture for the 80's. ITC 1984: 466-470 - Philip C. Jackson, Gregory de Mare, Albert Esser:
Compaction Technique Universal Pin Electronics. ITC 1984: 471-481
Session 15: Systems Test
- R. F. Voitus:
PBX System Test: Fast Functional Testing Without System Assembly. ITC 1984: 482-488 - Eric Sacher:
Component Level Fault-Isolation Techniques in a Systems Test Environment. ITC 1984: 489-492 - Todd Westerhoff, Andre DiMino:
The Role of the Engineering Work Station in Test Program Development. ITC 1984: 493-496 - James T. Healy:
An Information Processing Software System for ATE. ITC 1984: 497-505 - M. V. Limaye, K. Rajanikanth, H. S. Jamadagni:
Disc Drive Testing Instrument. ITC 1984: 506-512 - Gerard FitzPatrick, David F. Peach, Richard P. Cushman:
An Automated Test of a Disk Product Power System Independent of the Primary Function of the Machine. ITC 1984: 513-517
Session 16: How, Where, Why, and When of Lsi Burn-In
- Michael J. Campbell:
Monitored Burn-In (A Case Study for In-Situ Testing and Reliability Studies). ITC 1984: 518-523 - Anthony P. van den Heuvel, Noshir F. Khory:
A Rational Basis for Setting Burn-In Yield Criteria. ITC 1984: 524-530 - Eugene R. Hnatek:
Thoughts on VLSI Burn-in. ITC 1984: 531-535
Session 17: Advanced Probing Techniques for VLSI Devices
- Francois J. Henley:
An Automated Laser Prober to Determine VLSI Internal Node Logic States. ITC 1984: 536-542 - Y. Goto, K. Ozaki, T. Ishizuka, A. Ito, Y. Furukawa, T. Inagaki:
Electron Beam Prober for LSI Testing with 100ps Time Resolution. ITC 1984: 543-549 - P. Köllensperger, A. Krupp, Mathias Sturm, R. Weyl, F. Widulla, Eckhard Wolfgang:
Automated Electron Beam Testing of VLSI Circuits. ITC 1984: 550-557
Session 18: Advances In Board Test Techniques
- Stephen P. Denker, Judy Cobb:
Automatic Visual Testing: A New, Comprehensive Element of Cost-Effective PCB Testing Strategies. ITC 1984: 558-563 - Stephen R. Teta:
Using a Synchronous High-Speed Sensor System to Diagnose Microprocessor Boards. ITC 1984: 564-571 - Douglas W. Raymond:
In-Circuit Testability Factors: Shoot With a Rifle. ITC 1984: 572-580 - Stephen Caplow:
Conquering Testability Problems by Combining In-Circuit and Functional Techniques. ITC 1984: 581-588 - Mark S. Hoffman, Joseph F. Wrinn:
Channel Card Architecture for Multimode Board Test Systems. ITC 1984: 589-597 - Ramaswamy Balasubramaniam, Peretz Feder:
Test Strategy for a 32-Bit Microprocessor Module with Memory Management. ITC 1984: 598-605
Session 19: Software For Successful Test Systems
- Terence King:
Advanced Test System Software Architecture Blends High Speed with User Friendliness. ITC 1984: 606-613 - S. Daniel Lee, Tom Middleton:
Behavioral Simulation of VLSI Test System Aids Debugging and Analysis of Test Programs. ITC 1984: 614-620 - Vin Ratford, Mike Gill:
Software Verification Techniques. ITC 1984: 621-626 - G. Heretz, L. T. Matlock:
A Real-time Executive for a Distributed Processing System. ITC 1984: 627-629 - R. E. Kizis, G. C. Wickham:
Multi-Port Test Data Supply System. ITC 1984: 630-635 - Steven L. Watkins, Kenny Liu, Mitchell Schrift, Robert Patrie:
C : An Important Tool for Test Software Development. ITC 1984: 636-641
Session 20: VLSI Microprocessor Testing I
- Kenneth D. Mandl:
CMOS VLSI Challenges to Test. ITC 1984: 642-648 - Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes:
A Design for Machines with Built-In Tolerance to Soft Errors. ITC 1984: 649-659 - Tonysheng Lin, Stephen Y. H. Su:
Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique. ITC 1984: 660-668 - Scott Davidson:
Fault Simulation at the Architectural Level. ITC 1984: 669-679 - Catherine Bellon, Gabriele Saucier:
CADOC : A System for Computer Aided Functional Test. ITC 1984: 680-689
Session 21: Testability Analysis
- David M. Singer:
Testability Analysis of MOS VLSI Circuits. ITC 1984: 690-696 - Bill Underwood, M. Ray Mercer:
Correlating Testability with Fault Detection. ITC 1984: 697-704 - Franc Brglez, Philip Pownall, Robert Hum:
Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. ITC 1984: 705-712 - David M. Wu, Charles E. Radke, C. C. Beh:
Improve Yield and Quality Through Testability Analysis of VLSI Circuits. ITC 1984: 713-717 - Vishwani D. Agrawal:
Will Testability Analysis Replace Fault Simulation ? ITC 1984: 718-718 - J. Lawrence Carter:
A Vote in Favor of Fault Simulation. ITC 1984: 719-721 - Prabhakar Goel:
Testability Analysis will not Replace Fault Simulation. ITC 1984: 722-724 - F. C. Wang:
Testability Analysis: What Role Should it Play in IC Design ? ITC 1984: 725-727 - Robert Willoner:
The Importance of Fault Simulation. ITC 1984: 728-729
Session 22: Test Program Generation Tools
- Steve Broyles:
Automating Functional Programming for Micro-Based Boards. ITC 1984: 730-736 - Peter Hansen:
A Multimode Programming Strategy for VLSI Boards. ITC 1984: 737-742 - Robert G. Jacobson:
PAL and Logic Array In-Circuit Testing Considerations. ITC 1984: 743-746 - Herb Boulton:
Design Verification, Product Characterization and Production Testing of Hybrids and Printed Circuit Cards Using High-Sensitivity Thermography Systems. ITC 1984: 747-751 - Jeff Angwin, Paul Drake, Glenn Reader:
The Need for Real-Time Intelligence When Testing VLSI. ITC 1984: 752-761 - D. P. Ahrens, P. J. Bednarczyk, D. L. Denburg, R. M. Robertson:
TPG2 : An Automatic Test Program Generator for Custom ICs. ITC 1984: 762-767 - David Giles, Gregory A. Maston:
Device Models : A New Methodology for a Perennial Problem. ITC 1984: 768-772 - Edward S. Hirgelt:
Knowledge Representation in an In-Circuit Test Program Generator. ITC 1984: 773-777 - Beau R. Wilson Jr., Eugene R. Hnatek:
Problems Encountered in Developing VLSI Test Programs for COT (A Practical Outlook). ITC 1984: 778-788 - A. J. Kombol:
Processing of Test Data between Design and Testing. ITC 1984: 789-793
Session 24: VLSI Microprocessor Testing II
- Axel Hunger, Axel Gärtner:
Functional Characterization of Microprocessors. ITC 1984: 794-803 - Catherine Bellon, Raoul Velazco:
Hardware and Software Tools for Microprocessor Functional Test. ITC 1984: 804-820 - John Kuban, John Salick:
Testability Features of the MC68020. ITC 1984: 821-826 - Nobuo Arai, Yoshio Yamanaka:
Parallel Testing of Random Logic LSIs. ITC 1984: 827-833
Session 25: Design for Testability
- M. Gerner, Hans Nertinger:
Scan Path in CMOS Semicustom LSI Chips ? ITC 1984: 834-841 - Alfred K. Susskind:
A Technique for Making Asynchronous Sequential Circuits Readily Testable. ITC 1984: 842-846 - Bhargab B. Bhattacharya, Bidyut Gupta:
Logical Modeling of Physical Failures and Their Inherent Syndrome Testability in MOS LSI/VLSI Networks. ITC 1984: 847-855 - Saied Bozorgui-Nesbat, Edward J. McCluskey:
Lower Overhead Design for Testability of Programmable Logic Arrays. ITC 1984: 856-865 - Sridhar R. Manthani, Sudhakar M. Reddy:
On CMOS Totally Self-Checking Circuits. ITC 1984: 866-877 - Jon Turino:
A Totally Universal Reset, Initialization (and) Nodal Observation Circuit. ITC 1984: 878-884
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-31 20:22 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
