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ORCIDWeiwei Shi 0001
Person information
- affiliation: Shenzhen University, College of Information Engineering, China
- affiliation (PhD 2011): Chinese University of Hong Kong, Department of Electronic Engineering, Hong Kong
Other persons with the same name
- Weiwei Shi — disambiguation page
- Weiwei Shi 0002
![[0000-0001-8066-1519]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-8066-1519")
— Shanghai Jiao Tong University, School of Microelectronics, China - Weiwei Shi 0003 — Xi'an Jiaotong University, Institute of Artificial Intelligence and Robotics, China
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2020 – today
- 2023
[j8]Kezhu Liu, Weiwei Shi, Canji Huang, Dongdong Zeng:
Cost effective Tanh activation function circuits based on fast piecewise linear logic. Microelectron. J. 138: 105821 (2023)- [c17]Ziliang Yin, Weiwei Shi, Kezhu Liu:
An EEG Signal Processing System Design with Approximate Operations. ICTA 2023: 166-167 - 2022
- [j7]Weiwei Shi, Lizhi Hu, Yuan Liu, Sunbin Deng, Yuming Xu, Hoi-Sing Kwok, Rongsheng Chen:
Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 356-365 (2022) - [j6]Yongqian Su, Weiwei Shi, Lizhi Hu, Suixing Zhuang:
Implementation of SVM-Based Low Power EEG Signal Classification Chip. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4048-4052 (2022) - 2020
- [c16]Lizhi Hu, Yang Hong, Weiwei Shi, Mengtao Ye, Yongqian Su:
Pseudo-NMOS Logic Circuits using ITO-Stabilized ZnO TFTs. ICTA 2020: 85-87 - [c15]Yongqian Su, Yang Hong, Weiwei Shi, Mengtao Ye, Lizhi Hu:
Design of basic block of neural signal detection chip. ICTA 2020: 165-166
2010 – 2019
- 2019
- [j5]Weiwei Shi, Yuan Xu, Chiu-Sing Choy, Zhiyong Chen, Junwei Yang, Robert K. F. Teng, Mei Jiang, X. Deng:
A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1733-1737 (2019) - [c14]Zhiyong Chen, Weiwei Shi, Guoqiang Xiong, Junwei Yang, Yuan Xu:
A 63.3ps TDC Measurement System Based on FPGA for Pulsed Laser Ranging. ASICON 2019: 1-4 - [c13]Junwei Yang, Weiwei Shi, Zhiyu Huang, Yuan Xu, Yanghao Zheng, Xuanbin Fang:
A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF Application. ASICON 2019: 1-4 - 2018
- [j4]Hongda Wang, Weiwei Shi, Chiu-Sing Choy:
Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM. IEEE Access 6: 67277-67290 (2018) - [j3]Weiwei Shi, An Pan, Shi Yu, Chiu-sing Choy:
A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 159-167 (2018) - [j2]Weiwei Shi, Hai-Peng Wang, Chiu-Sing Choy, Junwei Yang, Mei Jiang, Robert K. F. Teng, Mingcheng Zhu:
A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1430-1434 (2018) - [c12]Weiwei Shi, An Pan:
Mixed Design of SPAD Array Based TOF for Depth Camera and Unmanned Vehicle Applications. SMACD 2018: 277-280 - 2017
- [c11]Hongda Wang, Weiwei Shi, Chiu-sing Choy:
Integrating channel selection and feature selection in a real time epileptic seizure detection system. EMBC 2017: 3206-3211 - 2016
- [c10]Weiwei Shi, Zhao Guangdong, Oliver Chiu-sing Choy:
Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells. ISVLSI 2016: 182-187 - [c9]Weiwei Shi, Chiu-sing Choy:
A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption. SoCC 2016: 125-128 - 2015
- [c8]Weiwei Shi, Linqing Fu, Chiu-sing Choy:
Subthreshold passive RFID tag's baseband processor core design with custom modules and cells. ICECS 2015: 45-48 - 2014
- [c7]Weiwei Shi, Oliver Chiu-sing Choy:
Subthreshold passive RF tag's PIE decoder design with wide tolerance and custom ratioed logic cells. ICECS 2014: 447-450 - [c6]Weiwei Shi, Oliver Chiu-sing Choy:
A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below. SoCC 2014: 54-57 - 2013
- [c5]Liwei Gong, Yuan Xu, Zhi Zhang, Weiwei Shi, Robert K. F. Teng:
An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technology. ASICON 2013: 1-4 - [c4]Weiwei Shi, Oliver Chiu-sing Choy, Robert K. F. Teng:
Key component designs of subthreshold baseband processors in passive RF device. ASICON 2013: 1-4 - 2012
- [c3]Weiwei Shi, Oliver Chiu-sing Choy:
A process-compatible passive RFID tag's digital design for subthreshold operation. ICECS 2012: 528-531 - 2010
- [j1]Ka Nang Leung, Chiu-sing Choy, Kong-Pang Pun, Lincoln Lai Kan Leung, Jianping Guo, Yuen Sum Ng, Chi Fat Chan, Weiwei Shi, Yang Hong, Marco Ho, Ki-Leung Mak, Yanqing Ai:
RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology. J. Low Power Electron. 6(1): 141-149 (2010)
2000 – 2009
- 2009
- [c2]Chi Fat Chan, Weiwei Shi, Kong-Pang Pun, Lincoln Lai Kan Leung, Ka Nang Leung, Oliver Chiu-sing Choy:
A Low-power Signal Processing Front-end and Decoder for UHF Passive RFID Transponders. ISCAS 2009: 1581-1584 - 2008
- [c1]Yang Hong, Chi Fat Chan, Jianping Guo, Yuen Sum Ng, Weiwei Shi, Lincoln Lai Kan Leung, Ka Nang Leung, Chiu-sing Choy, Kong-Pang Pun:
Design of passive UHF RFID tag in 130nm CMOS technology. APCCAS 2008: 1371-1374
Coauthor Index
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