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"Fast HUB Floating-Point Adder for FPGA."

Julio Villalba, Javier Hormigo, Sonia González-Navarro (2019)

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DOI: 10.1109/TCSII.2018.2873194

access: closed

type: Journal Article

metadata version: 2020-08-17

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  - https://dblp.org/rec/journals/tcas/VillalbaHG19
Julio Villalba, Javier Hormigo, Sonia González-Navarro:
Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(6): 1028-1032 (2019)

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