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"0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme."

Toshikazu Suzuki et al. (2010)

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DOI: 10.1109/ESSCIRC.2010.5619716

access: closed

type: Conference or Workshop Paper

metadata version: 2020-04-27

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Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara:
0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. ESSCIRC 2010: 354-357

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