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2020 – today
- 2022
[j60]Namhyung Kim
, Hanmin Park, Dongwoo Lee, Sungbum Kang, Jinho Lee, Kiyoung Choi:
ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator. IEEE Trans. Computers 71(7): 1537-1550 (2022)- [c132]Deokjin Lee, Kiyoung Choi, Wonbum Yun, Sehoon Oh:
Human-Robot Interaction Force based Power Assistive Algorithm of Upper Limb Exoskeleton Robots Driven by a Series Elastic Actuator. IECON 2022: 1-6 - 2021
- [c131]Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, Jinho Lee:
GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. HPCA 2021: 249-262 - [i4]Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, Jinho Lee:
GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. CoRR abs/2102.07511 (2021) - 2020
- [j59]Heesu Kim, Jongho Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, Kiyoung Choi, Hanmin Park:
Aging Compensation With Dynamic Computation Approximation. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1319-1332 (2020)
2010 – 2019
- 2019
- [c130]Joonsang Yu, Sungbum Kang, Kiyoung Choi:
Network Recasting: A Universal Method for Network Architecture Transformation. AAAI 2019: 5701-5708 - [c129]Hanmin Park, Kiyoung Choi:
Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators. ASP-DAC 2019: 286-291 - [c128]Gunhee Lee, Hanmin Park, Namhyung Kim, Joonsang Yu, Sujeong Jo, Kiyoung Choi:
Acceleration of DNN Backward Propagation by Selective Computation of Gradients. DAC 2019: 85 - [c127]Jongho Kim, Heesu Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, Kiyoung Choi:
Aging Gracefully with Approximation. ISCAS 2019: 1-5 - [c126]Jaehyun Kim, Chaeun Lee, Jihun Kim, Yumin Kim, Cheol Seong Hwang, Kiyoung Choi:
VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks. ISLPED 2019: 1-6 - [c125]Chaeun Lee, Jaehyun Kim, Kiyoung Choi:
An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network. ISOCC 2019: 259-260 - [i3]Euntae Choi, Kyungmi Lee, Kiyoung Choi:
Autoencoder-Based Incremental Class Learning without Retraining on Old Data. CoRR abs/1907.07872 (2019) - 2018
- [j58]Jaehyun Kim, Heesu Kim, Subin Huh, Jinho Lee, Kiyoung Choi:
Deep neural networks with weighted spikes. Neurocomputing 311: 373-386 (2018) - [j57]Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sánchez, Donghoon Yoo, Soojung Ryu:
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. ACM Trans. Archit. Code Optim. 15(1): 10:1-10:23 (2018) - [j56]Aidyn Zhakatayev, Kyounghoon Kim, Kiyoung Choi, Jongeun Lee:
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3056-3066 (2018) - [j55]Jongho Kim, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung-Hwan Choi:
Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 37-49 (2018) - [c124]Heesu Kim, Euntae Choi, Kiyoung Choi:
Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands. APSIPA 2018: 1766-1770 - [c123]Barend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi:
Architectures and algorithms for user customization of CNNs. ASP-DAC 2018: 540-547 - [c122]Sujeong Jo, Hanmin Park, Gunhee Lee, Kiyoung Choi:
Training Neural Networks with Low Precision Dynamic Fixed-Point. ICCD 2018: 405-408 - [c121]Dongwoo Lee, Sungbum Kang, Kiyoung Choi:
ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator. ICS 2018: 139-148 - [c120]Sungbum Kang, Joonsang Yu, Kiyoung Choi:
Tapered-Ratio Compression for Residual Network. ISOCC 2018: 72-73 - [c119]Hossein Moradian, Sujeong Jo, Kiyoung Choi:
Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators. ISOCC 2018: 212-213 - [c118]Jaehyun Kim, Chaeun Lee, Kiyoung Choi:
Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks. ISOCC 2018: 271-272 - [i2]Joonsang Yu, Sungbum Kang, Kiyoung Choi:
Network Recasting: A Universal Method for Network Architecture Transformation. CoRR abs/1809.05262 (2018) - 2017
- [j54]Mansureh Shahraki Moghaddam, M. Balakrishnan, Kiyoung Choi:
Optimal mapping of program overlays onto many-core platforms with limited memory capacity. Des. Autom. Embed. Syst. 21(3-4): 173-194 (2017) - [j53]Hyunjik Song, Kiyoung Choi:
Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(8): 1640-1649 (2017) - [j52]Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark Nutter, Damir A. Jamsek:
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. Proc. VLDB Endow. 10(12): 1706-1717 (2017) - [j51]Dongwoo Lee, Sang-Heon Lee, Soojung Ryu, Kiyoung Choi:
Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch. ACM Trans. Archit. Code Optim. 14(2): 11:1-11:25 (2017) - [j50]Jinho Lee, Jongwook Chung, Jung Ho Ahn, Kiyoung Choi:
Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1793-1806 (2017) - [c117]Hyeon Uk Sim, Dong Nguyen, Jongeun Lee, Kiyoung Choi:
Scalable stochastic-computing accelerator for convolutional neural networks. ASP-DAC 2017: 696-701 - [c116]Mansureh S. Moghaddam, Barend Harris, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi:
Incremental training of CNNs for user customization: work-in-progress. CASES 2017: 9:1-9:2 - [c115]Bernhard Egger, Hochan Lee, Duseok Kang, Mansureh S. Moghaddam, Youngchul Cho, Yeonbok Lee, Sukjin Kim, Soonhoi Ha, Kiyoung Choi:
A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures. CGO 2017: 197-209 - [c114]Atul Rahman, Sangyun Oh, Jongeun Lee, Kiyoung Choi:
Design space exploration of FPGA accelerators for convolutional neural networks. DATE 2017: 1147-1152 - [c113]Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeon Uk Sim, Jongeun Lee, Kiyoung Choi:
FPGA implementation of convolutional neural network based on stochastic computing. FPT 2017: 287-290 - [c112]Joonsang Yu, Kyounghoon Kim, Jongeun Lee, Kiyoung Choi:
Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks. ICCD 2017: 105-112 - [c111]Subin Huh, Joonsang Yu, Kiyoung Choi:
A new stochastic mutiplier for deep neural networks. ISOCC 2017: 46-47 - [c110]Kyounghoon Kim, Kiyoung Choi:
Synthesis of multi-variate stochastic computing circuits. VLSI-SoC 2017: 1-6 - [c109]Heesu Kim, Joonsang Yu, Kiyoung Choi:
Hybrid spiking-stochastic Deep Neural Network. VLSI-DAT 2017: 1-4 - [p2]Mansureh Shahraki Moghaddam, Jae-Min Cho, Kiyoung Choi:
Reconfigurable Architectures. Handbook of Hardware/Software Codesign 2017: 335-376 - 2016
- [j49]Hanmin Park, Kiyoung Choi:
Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip. IET Comput. Digit. Tech. 10(1): 37-44 (2016) - [j48]Namhyung Kim, Kiyoung Choi:
Exploration of trade-offs in the design of volatile STT-RAM cache. J. Syst. Archit. 71: 23-31 (2016) - [j47]Kyounghoon Kim, Helin Lin, Jin Young Choi, Kiyoung Choi:
A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers. Pattern Recognit. 52: 1-16 (2016) - [j46]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy. ACM Trans. Archit. Code Optim. 13(4): 34:1-34:24 (2016) - [j45]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture. IEEE Trans. Computers 65(3): 940-951 (2016) - [j44]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 453-464 (2016) - [c108]Kyounghoon Kim, Jongeun Lee, Kiyoung Choi:
An energy-efficient random number generator for stochastic circuits. ASP-DAC 2016: 256-261 - [c107]Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi:
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks. DAC 2016: 124:1-124:6 - [c106]Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung Yun Choi:
Adaptive delay monitoring for wide voltage-range operation. DATE 2016: 511-516 - [c105]Jinho Lee, Jung Ho Ahn, Kiyoung Choi:
Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic. DATE 2016: 1243-1248 - [c104]Atul Rahman, Jongeun Lee, Kiyoung Choi:
Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array. DATE 2016: 1393-1398 - [c103]Jungwoo Seo, Joonsang Yu, Jongeun Lee, Kiyoung Choi:
A new approach to binarizing neural networks. ISOCC 2016: 77-78 - [c102]Jaehyun Kim, Kiyoung Choi, Sang-Heon Lee, Soojung Ryu:
Dynamic clock synchronization scheme between voltage domains in multi-core architecture. VLSI-SoC 2016: 1-6 - [e5]Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis:
VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers. IFIP Advances in Information and Communication Technology 483, Springer 2016, ISBN 978-3-319-46096-3 [contents] - 2015
- [j43]Jinho Lee, Kyungsu Kang, Kiyoung Choi:
REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections. ACM J. Emerg. Technol. Comput. Syst. 12(3): 26:1-26:22 (2015) - [j42]Yiran Chen, Kiyoung Choi, Weisheng Zhao:
Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing. IEEE Trans. Multi Scale Comput. Syst. 1(3): 125-126 (2015) - [c101]Jinho Lee, Junwhan Ahn, Kiyoung Choi, Kyungsu Kang:
THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures. ASP-DAC 2015: 773-778 - [c100]Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
A scalable processing-in-memory accelerator for parallel graph processing. ISCA 2015: 105-117 - [c99]Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. ISCA 2015: 336-348 - [c98]Pierre Nicolas-Nicolaz, Kiyoung Choi:
Dynamic error tracking and supply voltage adjustment for low power. VLSI-SoC 2015: 74-79 - [c97]Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi:
Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. VLSI-SoC 2015: 183-188 - [c96]Naehyuck Chang, Kiyoung Choi:
Message from the general chairs. VLSI-SoC 2015: VIII - 2014
- [j41]Manhwee Jo, Dongwook Lee, Kyuseung Han, Kiyoung Choi:
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. Integr. 47(2): 232-241 (2014) - [j40]Kyuseung Han, Ganghee Lee, Kiyoung Choi:
Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture. IEEE Trans. Dependable Secur. Comput. 11(4): 392-398 (2014) - [j39]Jongeun Lee, Seongseok Seo, Jong Kyung Paek, Kiyoung Choi:
Configurable range memory for effective data reuse on programmable accelerators. ACM Trans. Design Autom. Electr. Syst. 19(2): 13:1-13:22 (2014) - [j38]Seokhyun Lee, Kiyoung Choi:
Critical-path-aware high-level synthesis with distributed controller for fast timing closure. ACM Trans. Design Autom. Electr. Syst. 19(2): 16:1-16:29 (2014) - [j37]Jason Helge Anderson, Kiyoung Choi:
Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12). ACM Trans. Reconfigurable Technol. Syst. 7(3): 18:1-18:2 (2014) - [j36]Junwhan Ahn, Kiyoung Choi:
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1197-1201 (2014) - [c95]Jihyun Ryoo, Kyuseung Han, Kiyoung Choi:
Leveraging parallelism in the presence of control flow on CGRAs. ASP-DAC 2014: 285-291 - [c94]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes. DAC 2014: 139:1-139:6 - [c93]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture. HPCA 2014: 25-36 - [c92]Helin Lin, Kyounghoon Kim, Kiyoung Choi:
Concept-aware ensemble system for pedestrian detection. Intelligent Vehicles Symposium 2014: 140-145 - [c91]Sungju Han, Jinho Lee, Kiyoung Choi:
Tree-Mesh Heterogeneous Topology for Low-Latency NoC. NoCArc@MICRO 2014: 19-24 - [c90]Dongwoo Lee, Kiyoung Choi:
Energy-efficient partitioning of hybrid caches in multi-core architecture. VLSI-SoC 2014: 1-6 - [c89]Dongwoo Lee, Kiyoung Choi:
Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture. VLSI-SoC (Selected Papers) 2014: 58-74 - [c88]Jae Min Cho, Kiyoung Choi:
An FPGA implementation of high-throughput key-value store using Bloom filter. VLSI-DAT 2014: 1-4 - 2013
- [j35]Kiyoung Choi, Sung-Up Jo, Hwamin Lee, Changsung Jeong:
CPU-based speed acceleration techniques for shear warp volume rendering. Multim. Tools Appl. 64(2): 309-329 (2013) - [j34]Kyuseung Han, Junwhan Ahn, Kiyoung Choi:
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. ACM Trans. Archit. Code Optim. 10(2): 8:1-8:25 (2013) - [j33]Junwhan Ahn, Kiyoung Choi:
Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 34-46 (2013) - [j32]Jinho Lee, Moo-Kyoung Chung, Yeon-Gon Cho, Soojung Ryu, Jung Ho Ahn, Kiyoung Choi:
Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1748-1761 (2013) - [j31]Jinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi:
Deflection routing in 3D network-on-chip with limited vertical bandwidth. ACM Trans. Design Autom. Electr. Syst. 18(4): 50:1-50:22 (2013) - [c87]Jinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi:
Deflection routing in 3D Network-on-Chip with TSV serialization. ASP-DAC 2013: 29-34 - [c86]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. ASP-DAC 2013: 285-290 - [c85]Kyuseung Han, Kiyoung Choi, Jongeun Lee:
Compiling control-intensive loops for CGRAs with state-based full predication. DATE 2013: 1579-1582 - [c84]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Write intensity prediction for energy-efficient non-volatile caches. ISLPED 2013: 223-228 - [c83]Gunhee Lee, Jinho Lee, Kiyoung Choi:
Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth. NoCArc@MICRO 2013: 23-26 - [c82]Manhwee Jo, Kyuseung Han, Kiyoung Choi:
Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture. MUE 2013: 1161-1167 - [c81]Jinho Lee, Kiyoung Choi:
A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections. NOCS 2013: 1-2 - 2012
- [j30]Kiyoung Choi, John Kim, Gabriel H. Loh:
Guest Editorial New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 121-123 (2012) - [j29]John Kim, Kiyoung Choi, Gabriel H. Loh:
Exploiting New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 124-136 (2012) - [j28]Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang:
ESL Design Methodology. J. Electr. Comput. Eng. 2012: 358281:1-358281:2 (2012) - [j27]Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi:
Active Memory Processor for Network-on-Chip-Based Architecture. IEEE Trans. Computers 61(5): 622-635 (2012) - [c80]Jinho Lee, Kiyoung Choi:
Memory-aware mapping and scheduling of tasks and communications on many-core SoC. ASP-DAC 2012: 419-424 - [c79]Kyuseung Han, Seongsik Park, Kiyoung Choi:
State-based full predication for low power coarse-grained reconfigurable architecture. DATE 2012: 1367-1372 - [c78]Junwhan Ahn, Kiyoung Choi:
Lower-bits cache for low power STT-RAM caches. ISCAS 2012: 480-483 - [c77]Dongwoo Lee, Junwhan Ahn, Kiyoung Choi:
A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem. ISOCC 2012: 159-162 - [c76]Di Wu, Junwhan Ahn, Imyong Lee, Kiyoung Choi:
Resource-shared custom instruction generation under performance/area constraints. ISSoC 2012: 1-6 - [c75]Hanmin Park, Kiyoung Choi:
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips. NoCArc@MICRO 2012: 51-56 - [c74]Mingyang Zhu, Jinho Lee, Kiyoung Choi:
An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth. VLSI-SoC 2012: 18-23 - 2011
- [j26]Kiyoung Choi:
Coarse-Grained Reconfigurable Array: Architecture and Application Mapping. IPSJ Trans. Syst. LSI Des. Methodol. 4: 31-46 (2011) - [j25]Ganghee Lee, Kiyoung Choi, Nikil D. Dutt:
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 637-650 (2011) - [c73]Junwhan Ahn, Imyong Lee, Kiyoung Choi:
A polynomial-time custom instruction identification algorithm based on dynamic programming. ASP-DAC 2011: 573-578 - [c72]Junwhan Ahn, Kiyoung Choi:
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. CODES+ISSS 2011: 345-354 - [c71]Hyunjik Song, Kiyoung Choi:
Simulated annealing-based diffusive load balancing on many-core SoC. ICAC 2011: 187-188 - [c70]Seokhyun Lee, Kiyoung Choi:
High-level synthesis with distributed controller for fast timing closure. ICCAD 2011: 193-199 - [c69]Jong Kyung Paek, Jong-eun Lee, Kiyoung Choi:
CRM: Configurable Range Memory for Fast Reconfigurable Computing. IPDPS Workshops 2011: 158-165 - [c68]Jinho Lee, Mingyang Zhu, Kiyoung Choi, Jung Ho Ahn, Rohit Sharma:
3D network-on-chip with wireless links through inductive coupling. ISOCC 2011: 353-356 - [c67]Yangsu Kim, Kyuseung Han, Kiyoung Choi:
A host-accelerator communication architecture design for efficient binary acceleration. ISOCC 2011: 361-364 - [c66]Jae Hong Park, Kiyoung Choi, Dong-Yeon Lee, Jaesool Shim, Tae Song Kim:
Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane. NEMS 2011: 61-63 - 2010
- [j24]Ganghee Lee, Yongjin Ahn, Seokhyun Lee, Jeongki Son, Kiwook Yoon, Kiyoung Choi:
Communication architecture design for reconfigurable multimedia SoC platform. Des. Autom. Embed. Syst. 14(1): 1-20 (2010) - [j23]Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee:
Binary acceleration using coarse-grained reconfigurable architecture. SIGARCH Comput. Archit. News 38(4): 33-39 (2010) - [j22]Yoonjin Kim, Rabi N. Mahapatra, Kiyoung Choi:
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1471-1482 (2010) - [c65]Ganghee Lee, Kiyoung Choi:
Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture. AHS 2010: 265-272 - [c64]Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt:
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. ARC 2010: 231-243 - [c63]Kyungwook Chang, Kiyoung Choi:
Memory-Centric Communication Architecture for Reconfigurable Computing. ARC 2010: 400-405 - [c62]Kyuseung Han, Jong Kyung Paek, Kiyoung Choi:
Acceleration of control flow on CGRA using advanced predicated execution. FPT 2010: 429-432 - [c61]