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ORCIDIvo Schanstra
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2000 – 2009
- 2004
[c10]Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor:
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. MTDT 2004: 32-37- 2003
- [c9]Ivo Schanstra, Ad J. van de Goor:
Consequences of RAM Bitline Twisting for Test Coverage. DATE 2003: 11176-11177 - 2002
- [c8]Ad J. van de Goor, Ivo Schanstra:
Address and Data Scrambling: Causes and Impact on Memory Tests. DELTA 2002: 128-136
1990 – 1999
- 1999
- [c7]Ad J. van de Goor, Ivo Schanstra:
Industrial evaluation of stress combinations for march tests applied to SRAMs. ITC 1999: 983-992 - 1998
- [c6]Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen:
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. ITC 1998: 872-881 - 1996
- [c5]Ad J. van de Goor, Aad Offerman, Ivo Schanstra:
Towards a Uniform Notation for Memory Tests. ED&TC 1996: 420-427 - 1995
- [c4]Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Functional test for shifting-type FIFOs. ED&TC 1995: 133-138 - 1994
- [c3]Ad J. van de Goor, Yervant Zorian, Ivo Schanstra:
Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC 1994: 666 - [c2]Yervant Zorian, Ad J. van de Goor, Ivo Schanstra:
An Effective BIST Scheme for Ring-Address Type FIFOs. ITC 1994: 378-387 - [c1]Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Fault models and tests for Ring Address Type FIFOs. VTS 1994: 300-305
Coauthor Index
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