Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm ..."

Rohit Pandey, Santanu Chattopadhyay (2003)

> Home

Details and statistics

DOI: 10.1109/ICVD.2003.1183118

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/PandeyC03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/PandeyC03
Rohit Pandey, Santanu Chattopadhyay:
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". VLSI Design 2003: 79-84

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.