"Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture."

Valerio Tenace et al. (2016)

> Home

Details and statistics

DOI: 10.1145/2902961.2902970

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/TenaceCMP16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/TenaceCMP16
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI 2016: 145-150

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.