default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI-SoC 2018: Verona, Italy - Selected Papers
- Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis:
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 561, Springer 2019, ISBN 978-3-030-23424-9 - Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. 1-13 - Shahzad Muzaffar, Ibrahim Abe M. Elfadel
:
An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication. 14-31 - Anna Bernasconi, Antonio Boffa, Fabrizio Luccio, Linda Pagli:
The Connection Layout in a Lattice of Four-Terminal Switches. 32-52 - Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Catalin Bogdan Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu:
Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS. 53-78 - Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu:
Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields. 79-106 - Valentino Peluso, Andrea Calimera:
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. 107-127 - Swagata Mandal, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay:
ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code. 128-146 - Md. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori:
Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems. 147-166 - Francesco Barchi, Gianvito Urgese, Enrico Macii, Andrea Acquaviva:
Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis. 167-186 - Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda, Jan-Gerd Mess:
Improved Test Solutions for COTS-Based Systems in Space Applications. 187-206 - Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy:
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. 207-231 - Xiaorui Liu, Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos:
Assessment of Low-Budget Targeted Cyberattacks Against Power Systems. 232-256 - Tim Fritzmann, Thomas Schamberger, Christoph Frisch, Konstantin Braun, Georg Maringer, Johanna Sepúlveda:
Efficient Hardware/Software Co-design for NTRU. 257-280
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-01 20:51 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
