"Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage ..."

Enrico Macii et al. (2008)

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DOI: 10.1109/DSD.2008.90

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino:
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD 2008: 298-303

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