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ORCIDPaul E. Gronowski
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2010 – 2019
- 2011
[c2]Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski:
A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. ISSCC 2011: 84-86
2000 – 2009
- 2009
- [j5]Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer:
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. IEEE J. Solid State Circuits 44(1): 18-31 (2009) - 2008
- [c1]Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles:
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor. ISSCC 2008: 92-93
1990 – 1999
- 1998
- [j4]Paul E. Gronowski, William J. Bowhill, Ronald P. Preston, Michael K. Gowan, Randy L. Allmon:
High-performance microprocessor design. IEEE J. Solid State Circuits 33(5): 676-686 (1998) - 1996
- [j3]Paul E. Gronowski, William J. Bowhill, Dale R. Donchin, Randel P. Blake-Campos, David A. Carlson, Edward R. Equi, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Andy Olesin, Date J. W. Noorlag, Ronald P. Preston:
A 433-MHz 64-b quad-issue RISC microprocessor. IEEE J. Solid State Circuits 31(11): 1687-1696 (1996) - 1995
- [j2]William J. Bowhill, Shane L. Bell, Bradley J. Benschneider, Andrew J. Black, Sharon M. Britton, Ruben W. Castelino, Dale R. Donchin, John H. Edmondson, Harry R. Fair III, Paul E. Gronowski, Anil K. Jain, Patricia L. Kroesen, Marc E. Lamere, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Ronald P. Preston, Sribalan Santhanam, Timothy A. Shedd, Michael J. Smith, Stephen C. Thierauf:
Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU. Digit. Tech. J. 7(1) (1995) - [j1]Bradley J. Benschneider, Andrew J. Black, William J. Bowhill, Sharon M. Britton, Daniel E. Dever, Dale R. Donchin, Robert J. Dupcak, Richard M. Fromm, Mary K. Gowan, Paul E. Gronowski, Michael Kantrowitz, Marc E. Lamere, Shekhar Mehta, Jeanne E. Meyer, Robert O. Mueller, Andy Olesin, Ronald P. Preston, Donald A. Priore, Sribalan Santhanam, Michael J. Smith, Gilbert M. Wolrich:
A 300-MHz 64-b quad-issue CMOS RISC microprocessor. IEEE J. Solid State Circuits 30(11): 1203-1214 (1995)
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