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"A 286 MHz 64-b floating point multiplier with enhanced CG operation."

Hiroshi Makino et al. (1996)

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DOI: 10.1109/4.499726

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - https://dblp.org/rec/journals/jssc/MakinoSMNMS96
Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31(4): 504-513 (1996)

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