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"Optimal wire sizing and buffer insertion for low power and a generalized ..."

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin (1996)

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DOI: 10.1109/4.494206

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - journals/jssc/LillisCL96
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  - https://dblp.org/rec/journals/jssc/LillisCL96
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid State Circuits 31(3): 437-447 (1996)

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