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"A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic ..."

Keiichi Higeta et al. (1996)

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DOI: 10.1109/4.540054

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - journals/jssc/HigetaUOFNIYINO96
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  - https://dblp.org/rec/journals/jssc/HigetaUOFNIYINO96
Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta:
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. IEEE J. Solid State Circuits 31(10): 1443-1450 (1996)

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