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"2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 ..."

Masakazu Kurisu et al. (1996)

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DOI: 10.1109/4.545826

access: closed

type: Journal Article

metadata version: 2022-10-02

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  - journals/jssc/KurisuKSTTFTNY96
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  - https://dblp.org/rec/journals/jssc/KurisuKSTTFTNY96
Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida:
2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology. IEEE J. Solid State Circuits 31(12): 2024-2029 (1996)

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