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2020 – today
- 2023
[j5]Jin-Yi Lin
, Shu-Yen Lin:
Temperature-Prediction Based Rate-Adjusted Time and Space Mapping Algorithm for 3D CNN Accelerator Systems. IEEE Trans. Computers 72(10): 2767-2780 (2023)- [c12]Jin-Yi Lin, Yan-Ren Ban, Ching-Ting Hsu, Wei Hua Ho, Pao-Hung Chung:
A Weightlifting Clean and Jerk Team Formation Model by Considering Barbell Trajectory and LSTM Neural Network. HCI (41) 2023: 542-553 - [c11]Ming-Che Chen, Hsin-Hsu Chou, Hsiag-Chun Chen, Jin-Yi Lin, Ren-Guei Hsu, Jia-Xiang Chen, Yu-Tse Lee, Jung-Yao Zhuo, Wan-Jung Chang, Yang-Kun Ou:
iCAPD: A Deep Learning-Based Monitoring System for Continuous Ambulatory Peritoneal Dialysis. ICCE-Taiwan 2023: 657-568
2010 – 2019
- 2019
- [c10]Shu-Yen Lin, Jin-Yi Lin:
Dynamic Thermal-Aware Inter-Layer Perpendicular Downward Mapping for Three-Dimensional Convolutional Neural Network Accelerator. GCCE 2019: 527-528 - 2017
- [j4]Shu-Yen Lin, Jin-Yi Lin:
Thermal- and Performance-Aware Address Mapping for the Multi-Channel Three-Dimensional DRAM Systems. IEEE Access 5: 5566-5577 (2017) - [j3]Jin-Yi Lin, Chih-Cheng Hsieh:
A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(3): 562-572 (2017) - 2016
- [j2]Pei-Chen Lee, Jin-Yi Lin, Chih-Cheng Hsieh:
A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12): 2149-2157 (2016) - [c9]Shu-Yen Lin, Jin-Yi Lin, Cheng-Hung Lin:
A reconfigurable near-data systolic array accelerator for the three-dimensional DRAM systems. GCCE 2016: 1-2 - [c8]Hung-Wen Lin, Jin-Yi Lin:
A passband lock loop circuit system for band pass filter. ISOCC 2016: 111-112 - 2015
- [j1]Jin-Yi Lin, Chih-Cheng Hsieh:
A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 70-79 (2015) - [c7]Shu-Yen Lin, Jin-Yi Lin, Kai-Wei Chang, Cheng-Hung Huang:
Real-time data compression for thermal-controlled three-dimensional DRAM systems. GCCE 2015: 48-49 - [c6]Jin-Yi Lin, Kwuang-Han Chang, Chen-Che Kao, Shih-Chin Lo, Yan-Jiun Chen, Pei-Chen Lee, Chi-Hui Chen, Chin Yin, Chih-Cheng Hsieh:
An 8-bit column-shared SAR ADC for CMOS image sensor applications. ISCAS 2015: 301-304 - 2014
- [c5]Shu-Yen Lin, Jin-Yi Lin:
Thermal-aware architecture and mapping for multi-channel three-dimensional DRAM systems. GCCE 2014: 713-714 - [c4]Hung-Wen Lin, Jin-Yi Lin, Min-Tai Chuang:
A low-area digitalized channel selection filter for DSRC system. VLSI-DAT 2014: 1-4 - 2012
- [c3]Hsin-Yuan Huang, Jin-Yi Lin, Chih-Cheng Hsieh, Wen-Hsu Chang, Hann-Huei Tsai, Chin-Fong Chiu:
A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching. ISCAS 2012: 2353-2356 - 2011
- [c2]Shang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh, Ka-Yi Yeh, Chung-Chi Jim Li:
A new CMOS image sensor readout structure for 3D integrated imagers. CICC 2011: 1-4 - [c1]Yin-Tien Wang, Shi-Hao Wang, Ying-Chieh Feng, Jin-Yi Lin:
Robot Pose and Velocity Estimation Using a Binocular Vision. FIRA 2011: 140-146
Coauthor Index
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