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ORCIDFPT 2017: Melbourne, Australia
- International Conference on Field Programmable Technology, FPT 2017, Melbourne, Australia, December 11-13, 2017. IEEE 2017, ISBN 978-1-5386-2656-6
Architecture
- Junqi Yuan, Lingli Wang, Xuegong Zhou, Yinshui Xia, Jianping Hu:
RBSA: Range-based simulated annealing for FPGA placement. 1-8 - Sadegh Yazdanshenas, Vaughn Betz:
Automatic circuit design and modelling for heterogeneous FPGAs. 9-16 - Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt:
Liquid: High quality scalable placement for large heterogeneous FPGAs. 17-24 - Harald Homulle
, Edoardo Charbon:
Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures. 25-31
Memory & I/O
- Dan Cristian Turicu, Octavian Cret, Lucia Vacariu:
High performance serial ATA Gen3 controllers on FPGA devices. 32-39 - Wei Li, Yangyang Zhao, Yuhang Liu, Mingyu Chen:
SMEFF: A scalable memory extension fabric for FPGA. 40-47 - William Kamp:
AXI over Ethernet; a protocol for the monitoring and control of FPGA clusters. 48-55 - Justin S. J. Wong, Runbin Shi, Maolin Wang, Hayden Kwok-Hay So:
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory. 56-63
Libraries & Synthesis
- Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre:
HopliteRT: An efficient FPGA NoC for real-time applications. 64-71 - He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-precision constant-hardware iterative compute. 73-79 - Shadi Assadikhomami, Jennifer Ongko, Tor M. Aamodt:
A state machine block for high-level synthesis. 80-87 - Lekhobola J. Tsoeunyane, Simon Winberg, Michael Inggs:
An IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patterns. 88-95
Productivity & Tooling
- Shaoyi Cheng, Qijing Huang, John Wawrzynek:
Synthesis of program binaries into FPGA accelerators with runtime dependence validation. 96-103 - Felix Winterstein, George A. Constantinides:
Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs. 104-111 - Prajith Ramakrishnan Geethakumari, Vincenzo Gulisano, Bo Joel Svensson, Pedro Trancoso, Ioannis Sourdis:
Single window stream aggregation using reconfigurable hardware. 112-119
Crypto & Networking
- Ekawat Homsirikamol, Kris Gaj:
Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study. 120-127 - William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj:
Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs. 128-135 - Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura:
Accelerating NFV application using CPU-FPGA tightly coupled architecture. 136-143
ML/Vision I
- Hai Peng, Xiaofan Zhang, Letian Huang:
An energy efficient approach for C4.5 algorithm using OpenCL design flow. 144-151 - Hossein Omidian, Guy G. F. Lemieux:
Exploring automated space/time tradeoffs for OpenVX compute graphs. 152-159 - Sam M. H. Ho, Hayden Kwok-Hay So:
NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs. 160-167
ML/Vision II
- Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato:
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. 168-175 - Siew-Kei Lam, Rakesh Kumar Bijarniya, Meiqing Wu:
Lowering dynamic power in stream-based harris corner detection architecture. 176-182 - Rongdi Sun, Peilin Liu, Jun Wang, Cecil Accetti, Abid A. Naqvi:
A 42fps full-HD ORB feature extraction accelerator with reduced memory overhead. 183-190
Poster
- Moucheng Yang, Jifang Jin, Zhehao Li, Xuegong Zhou, Shaojun Wang, Lingli Wang:
A scalable hybrid architecture for high performance data-parallel applications. 191-194 - Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday:
Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs. 195-198 - Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis:
Model-based hardware design based on compatible sets of isomorphic subgraphs. 199-202 - Amit Kulkarni, Poona Bahrebar, Dirk Stroobandt, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu:
A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration. 203-206 - Zhiqiang Liu, Yong Dou, Jingfei Jiang, Qiang Wang, Paul Chow:
An FPGA-based processor for training convolutional neural networks. 207-210 - Kentaro Katayama, Hidetoshi Matsumura, Hiroaki Kameyama, Shinichi Sazawa, Yasuhiro Watanabe:
An FPGA-accelerated high-throughput data optimization system for high-speed transfer via wide area network. 211-214 - Nam Ho, Paul Kaufmann, Marco Platzner:
Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. 215-218 - Andrew Ang, Matt Bourne, Robin Dykstra:
An open source PXIe ecosystem based on FPGA modules. 219-222 - Ke Cui, Zongkai Liu, Rihong Zhu, Xiangyu Li:
FPGA-based high-performance time-to-digital converters by utilizing multi-channels looped carry chains. 223-226 - Jincheng Yu, Yiming Hu, Xuefei Ning, Jiantao Qiu, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA. 227-230 - Weijia Li, Conghui He, Haohuan Fu, Wayne Luk:
An FPGA-based tree crown detection approach for remote sensing images. 231-234 - Ahmad Salman, William Diehl, Jens-Peter Kaps:
A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption. 235-238 - Roberto DiCecco, Lin Sun, Paul Chow:
FPGA-based training of convolutional neural networks with a reduced precision floating-point library. 239-242 - Brian Jarvis, Kris Gaj:
Selection of an error-correcting code for FPGA-based physical unclonable functions. 243-246 - Baofu Zhao, Yubin Li, Yu Wang, Huazhong Yang:
Streaming sorting network based BWT acceleration on FPGA for lossless compression. 247-250 - P. M. K. Tharaka, D. M. D. Wijerathne, Navoda Perera, Dinushan Vishwajith, Ajith Pasqual:
Runtime rule-reconfigurable high throughput NIPS on FPGA. 251-254 - Artur Podobas, Satoshi Matsuoka:
Designing and accelerating spiking neural networks using OpenCL for FPGAs. 255-258 - Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra:
Customizable FPGA OpenCL matrix multiply design template for deep neural networks. 259-262 - Brice Colombier, Lilian Bossuet, Ugo Mureddu, David Hély:
A comprehensive hardware/software infrastructure for IP cores design protection. 263-266 - Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. 267-270 - Erik H. D'Hollander, Bruno Chevalier, Koen De Bosschere:
Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA. 271-274 - Weikang Fang, Yanjun Zhang, Bo Yu, Shaoshan Liu:
FPGA-based ORB feature extraction for real-time visual SLAM. 275-278
Demo Session
- Dong Wang, Ke Xu, Diankun Jiang:
PipeCNN: An OpenCL-based open-source FPGA accelerator for convolution neural networks. 279-282 - Donald G. Bailey:
Hough transform line reconstruction on FPGA using back-projection. 283-286 - Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeon Uk Sim, Jongeun Lee, Kiyoung Choi:
FPGA implementation of convolutional neural network based on stochastic computing. 287-290
Design Competition
- Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
All binarized convolutional neural network and its implementation on an FPGA. 291-294 - Mankit Sit, Ryosuke Kazami, Hideharu Amano:
FPGA-based accelerator for losslessly quantized convolutional neural networks. 295-298
PhD Forum
- Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri:
FPGA implementation of a real-time super-resolution system with a CNN based on a residue number system. 299-300 - Bingyi Li, Linlin Fang, Yizhuang Xie, He Chen, Liang Chen:
A unified reconfigurable floating-point arithmetic architecture based on CORDIC algorithm. 301-302
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