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ORCIDReConFig 2019: Cancun, Mexico
- David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner:
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019. IEEE 2019, ISBN 978-1-7281-1957-1 - David Wilson, Greg Stitt:
Seiba: An FPGA Overlay-Based Approach to Rapid Application Development. 1-8 - Ariel Podlubne, Diana Göhringer
:
FPGA-ROS: Methodology to Augment the Robot Operating System with FPGA Designs. 1-5 - Tomohiro Kida, Yuichi Kawamata, Yuichiro Shibata, Kentaro Sano:
A High Level Synthesis Approach for Application Specific DMA Controllers. 1-2 - Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin:
Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs. 1-2 - Ali Mirzaeian, Houman Homayoun, Avesta Sasan:
TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs. 1-8 - Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Norbert Wehn, Andreas Dengel:
iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction. 1-8 - Michal Andrzejczak, Farnoud Farahmand, Kris Gaj:
Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5. 1-2 - Sen Ma, Shanyuan Gao:
The Impact of Adopting Computational Storage in Heterogeneous Computing Systems. 1-8 - Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf:
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. 1-8 - Samah Rahamneh, Lina Sawalha:
Efficient OpenCL Accelerators for Canny Edge Detection Algorithm on a CPU-FPGA Platform. 1-5 - Beck Strohmer, Anders Bøgild, Anders Stengaard Sørensen, Leon Bonde Larsen:
ROS-Enabled Hardware Framework for Experimental Robotics. 1-2 - Siavash Rezaei, Eli Bozorgzadeh, Kanghee Kim:
UltraShare: FPGA-based Dynamic Accelerator Sharing and Allocation. 1-5 - Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara:
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. 1-5 - Nils Voss, Stephen Girdlestone, Tobias Becker, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev:
Low Area Overhead Custom Buffering for FFT. 1-8 - Atiyehsadat Panahi, Keaten Stokke, David Andrews:
A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs. 1-8 - Sina Boroumand, Philip Brisk:
Approximate Adder Tree Synthesis for FPGAs. 1-8 - Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. 1-8 - Regina Marcela Ivo, Daniel M. Muñoz:
RTRLib: A High-Level Modeling Tool for the Implementation of Dynamically Partial Reconfigurable System-on-Chips. 1-5 - Tolga Yalçin, Elif Bilge Kavun:
Almost-Zero Logic Implementation of Troika Hash Function on Reconfigurable Devices. 1-6 - Caleb Donovick, Makai Mann, Clark W. Barrett, Pat Hanrahan:
Agile SMT-Based Mapping for CGRAs with Restricted Routing Networks. 1-8 - Corbin Thurlow, Hayden Rowberry, Michael J. Wirthlin:
TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs. 1-8 - Muhammad Mudussir Ayub, Habibullah Ahmadzay, Josef Eckmüller, Franz Kreupl:
Electronic System Level Power and Performance Analysis for Multi-Processor-System-on-Chip. 1-2 - Abdelrahman Elkanishy, Derrick T. Rivera, Paul M. Furth, Abdel-Hameed A. Badawy, Youssef Aly, Christopher P. Michael:
FPGA-Accelerated Decision Tree Classifier for Real-Time Supervision of Bluetooth SoC. 1-5 - Burak Unal, Md Sahil Hassan, Joshua Mack, Nirmal Kumbhare, Ali Akoglu:
Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes. 1-8 - Wesley Stirk, Jeffrey Goeders:
Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis. 1-5 - Abubakr Abdulgadir, William Diehl, Jens-Peter Kaps:
An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers. 1-5 - Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia, Philippe Loubet-Moundi:
High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs. 1-8 - Kevin Millar, Marcin Lukowiak, Stanislaw P. Radziszowski:
Design of a Flexible Schönhage-Strassen FFT Polynomial Multiplier with High- Level Synthesis to Accelerate HE in the Cloud. 1-5 - Abhi D. Rajagopala, Ron Sass, Andrew G. Schmidt:
Volcan: System Integration of HLS and HMC on FPGAs. 1-2 - Ismael-Antonio Dávila-Rodríguez, Marco Aurelio Nuño-Maganda, Yahir Hernandez-Mier, Said Polanco-Martagón:
Decision-Tree Based Pixel Classification for Real-time Citrus Segmentation on FPGA. 1-8 - Sunwoong Kim, Keewoo Lee, Wonhee Cho, Jung Hee Cheon, Rob A. Rutenbar:
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption. 1-8 - Tomás Benes, Matej Bartík, Pavel Kubalík:
High Throughput and Low Latency LZ4 Compressor on FPGA. 1-5 - Tatsuya Kaneko, Hiroshi Momose, Tetsuya Asai:
An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm. 1-8 - Carsten Heinz, Yannick Lavan, Jaco A. Hofmann, Andreas Koch:
A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors. 1-8 - Andrei Hagiescu, Martin Langhammer, Bogdan Pasca, Philip Colangelo, Jason Thong, Niayesh Ilkhani:
BFLOAT MLP Training Accelerator for FPGAs. 1-5 - Adrian Tatulian, Soheil Salehi, Ronald F. DeMara:
Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing. 1-8 - Cristian Urlea, Wim Vanderbauwhede, Syed Waqar Nabi:
Efficient FPGA Cost-Performance Space Exploration using Type-Driven Program Transformations. 1-2 - Guilherme Korol, Michael Guilherme Jordan, Raul Silveira Silva, Monica Magalhães Pereira, Marcelo Brandalero, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
A Runtime Power-Aware Phase Predictor for CGRAs. 1-8 - Arkan Alkamil, Darshika G. Perera:
Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded Platforms. 1-8 - Habib ul Hasan Khan, Gökhan Akgün, Ariel Podlubne, Felix Wegener, Amir Moradi, Diana Göhringer:
Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems. 1-5 - Ievgen Kabin, Alejandro Sosa, Zoya Dyka, Dan Klann, Peter Langendörfer:
On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack. 1-5 - Andrew E. Wilson, Michael J. Wirthlin:
Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAs. 1-7
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