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ORCIDMateo Valero
Mateo Valero Cortés
Person information
- affiliation: Polytechnic University of Catalonia, Barcelona, Spain
- award (2012): ACM Distinguished Service Award
- award (2009): Harry H. Goode Memorial Award
- award (2007): Eckert-Mauchly Award
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2020 – today
- 2023
[j139]Francesco Minervini
, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal:
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. ACM Trans. Archit. Code Optim. 20(2): 28:1-28:25 (2023)- [c341]Julián Pavón, Iván Vargas Valdivieso, Joan Marimon, Roger Figueras, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal:
VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing. HPCA 2023: 1289-1302 - 2022
- [c340]Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francesc Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa:
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. DCIS 2022: 1-6 - [c339]Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis A. Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal:
Adaptable Register File Organization for Vector Processors. HPCA 2022: 786-799 - 2021
- [j138]Ulises Cortés, Eduardo Ulises Moya-Sánchez, Mateo Valero:
When Sally Met Harry or When AI Met HPC. Supercomput. Front. Innov. 8(1): 4-7 (2021) - [c338]Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero:
PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy. Euro-Par 2021: 599-615 - [c337]Julian Pavon, Iván Vargas Valdivieso, Adrián Barredo, Joan Marimon, Miquel Moretó, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal:
VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations. HPCA 2021: 921-934 - [c336]Veljko M. Milutinovic, Erfan Sadeqi Azer, Kristy Yoshimoto, Gerhard Klimeck, Miljan Djordjevic, Milos Kotlar, Miroslav Bojovic, Bozidar Miladinovic, Nenad Korolija, Stevan Stankovic, Nenad Filipovic, Zoran Babovic, Miroslav Kosanic, Akira Tsuda, Mateo Valero, Massimo De Santo, Erich J. Neuhold, Jelena Skorucak, Laura Dipietro, Ivan Ratkovic:
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing. MECO 2021: 1-6 - [i5]Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis Alfonso Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal:
Adaptable Register File Organization for Vector Processors. CoRR abs/2111.05301 (2021) - 2020
- [j137]Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero:
Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. Future Gener. Comput. Syst. 112: 832-847 (2020) - [j136]Damian Roca, Rodolfo A. Milito, Mario Nemirovsky, Mateo Valero:
Advances in the Hierarchical Emergent Behaviors (HEB) Approach to Autonomous Vehicles. IEEE Intell. Transp. Syst. Mag. 12(4): 57-65 (2020) - [j135]Adrián Barredo, Juan M. Cebrian, Mateo Valero, Marc Casas, Miquel Moretó:
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. J. Supercomput. 76(3): 1960-1979 (2020) - [j134]Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Using Arm's scalable vector extension on stencil codes. J. Supercomput. 76(3): 2039-2062 (2020) - [c335]Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa:
An Academic RISC-V Silicon Implementation Based on Open-Source Components. DCIS 2020: 1-6 - [c334]Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. HPCA 2020: 717-728 - [c333]Javier Ferrando, Juan Luis Domínguez, Jordi Torres, Raúl García, David García, Daniel Garrido, Jordi Cortada, Mateo Valero:
Improving Accuracy and Speeding Up Document Image Classification Through Parallel Systems. ICCS (2) 2020: 387-400 - [c332]Vladimir Dimic, Miquel Moretó, Marc Casas, Jan Ciesko, Mateo Valero:
RICH: implementing reductions in the cache hierarchy. ICS 2020: 16:1-16:13 - [c331]Luc Jaulmes, Miquel Moretó, Mateo Valero, Mattan Erez, Marc Casas:
Runtime-guided ECC protection using online estimation of memory vulnerability. SC 2020: 76 - [i4]Javier Ferrando, Juan Luis Domínguez, Jordi Torres, Raúl García, David García, Daniel Garrido, Jordi Cortada, Mateo Valero:
Improving accuracy and speeding up Document Image Classification through parallel systems. CoRR abs/2006.09141 (2020) - [i3]Veljko Milutinovic, Milos Kotlar, Ivan Ratkovic, Nenad Korolija, Miljan Djordjevic, Kristy Yoshimoto, Erik Klem, Mateo Valero:
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chips. CoRR abs/2009.10593 (2020)
2010 – 2019
- 2019
- [j133]Fabrizio Gagliardi, Miquel Moretó, Mauro Olivieri, Mateo Valero:
The international race towards Exascale in Europe. CCF Trans. High Perform. Comput. 1(1): 3-13 (2019) - [j132]Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero:
Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications. Int. J. Parallel Program. 47(3): 343-344 (2019) - [j131]Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Mateo Valero:
On the maturity of parallel applications for asymmetric multi-core processors. J. Parallel Distributed Comput. 127: 105-115 (2019) - [j130]Xubin Tan, Jaume Bosch, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero:
A Hardware Runtime for Task-Based Programming Models. IEEE Trans. Parallel Distributed Syst. 30(9): 1932-1946 (2019) - [c330]Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
POSTER: An Optimized Predication Execution for SIMD Extensions. PACT 2019: 479-480 - [c329]Dimitrios Chasapis, Miquel Moretó, Martin Schulz, Barry Rountree, Mateo Valero, Marc Casas:
Power efficient job scheduling by predicting the impact of processor manufacturing variability. ICS 2019: 296-307 - [c328]Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs. ICS 2019: 380-391 - [c327]Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
A Vulnerability Factor for ECC-protected Memory. IOLTS 2019: 176-181 - [c326]Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs: poster. PPoPP 2019: 415-416 - 2018
- [j129]Daniel Nemirovsky, Tugberk Arkose, Nikola Markovic, Mario Nemirovsky, Osman S. Unsal, Adrián Cristal, Mateo Valero:
A General Guide to Applying Machine Learning to Computer Architecture. Supercomput. Front. Innov. 5(1): 95-115 (2018) - [j128]Helena Caminal, Diego Caballero, Juan M. Cebrian, Roger Ferrer, Marc Casas, Miquel Moretó, Xavier Martorell, Mateo Valero:
Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. J. Supercomput. 74(6): 2627-2637 (2018) - [j127]Paul Caheny, Lluc Alvarez, Said Derradji, Mateo Valero, Miquel Moretó, Marc Casas:
Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. IEEE Trans. Parallel Distributed Syst. 29(5): 1174-1187 (2018) - [j126]Luc Jaulmes, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers. IEEE Trans. Parallel Distributed Syst. 29(9): 1961-1974 (2018) - [j125]Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero:
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 639-652 (2018) - [c325]Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Stencil codes on a vector length agnostic architecture. PACT 2018: 13:1-13:12 - [c324]Emilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Mateo Valero:
Architectural Support for Task Dependence Management with Flexible Software Scheduling. HPCA 2018: 283-295 - [c323]Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies. ICS 2018: 207-217 - [c322]Lluc Alvarez, Marc Casas, Jesús Labarta, Eduard Ayguadé, Mateo Valero, Miquel Moretó:
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs. ICS 2018: 218-228 - [c321]Mateo Valero Cortés:
Runtime Aware Architectures. SIGSIM-PADS 2018: 3-4 - [c320]Isaac Sánchez Barrera, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Graph partitioning applied to DAG scheduling to reduce NUMA effects. PPoPP 2018: 419-420 - [c319]Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moretó, Marc Casas:
Runtime-assisted cache coherence deactivation in task parallel programs. SC 2018: 35:1-35:12 - [e9]Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero:
Network and Parallel Computing - 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29 - December 1, 2018, Proceedings. Lecture Notes in Computer Science 11276, Springer 2018, ISBN 978-3-030-05676-6 [contents] - [i2]Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
Memory Vulnerability: A Case for Delaying Error Reporting. CoRR abs/1810.06472 (2018) - 2017
- [j124]Pablo Fuentes, Mariano Benito, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Andreea Anghel, Germán Rodríguez, Mitch Gusat, Cyriel Minkenberg, Mateo Valero:
A scalable synthetic traffic model of Graph500 for computer networks analysis. Concurr. Comput. Pract. Exp. 29(24) (2017) - [j123]Vesna Smiljkovic, Osman S. Ünsal, Adrián Cristal, Mateo Valero:
Determinism at Standard-Library Level in TM-Based Applications. Int. J. Parallel Program. 45(1): 17-29 (2017) - [j122]Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Adrián Cristal, Osman S. Unsal, Mateo Valero:
An Integrated Vector-Scalar Design on an In-Order ARM Core. ACM Trans. Archit. Code Optim. 14(2): 17:1-17:26 (2017) - [j121]Kallia Chronaki, Alejandro Rico, Marc Casas, Miquel Moretó, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Task Scheduling Techniques for Asymmetric Multi-Core Systems. IEEE Trans. Parallel Distributed Syst. 28(7): 2074-2087 (2017) - [c318]Daniel Nemirovsky, Tugberk Arkose, Nikola Markovic, Mario Nemirovsky, Osman S. Unsal, Adrián Cristal, Mateo Valero:
A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems. CARLA 2017: 3-20 - [c317]Mateo Valero:
Runtime Aware Architectures. Conf. Computing Frontiers 2017 - [c316]Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero:
Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals. Euro-Par 2017: 247-259 - [c315]Esteban Stafford, Borja Pérez, José Luis Bosque, Ramón Beivide, Mateo Valero:
To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy. Euro-Par 2017: 710-722 - [c314]Lluís Vilanova, Marc Jordà, Nacho Navarro, Yoav Etsion, Mateo Valero:
Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC. EuroSys 2017: 16-31 - [c313]Damian Roca, Josue V. Quiroga, Mateo Valero, Mario Nemirovsky:
Fog Function Virtualization: A flexible solution for IoT applications. FMEC 2017: 74-80 - [c312]Xubin Tan, Jaume Bosch, Miquel Vidal, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero:
Picos, A Hardware Task-Dependence Manager for Task-Based Dataflow Programming Models. HPCS 2017: 878-880 - [c311]Xubin Tan, Jaume Bosch, Miquel Vidal, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero:
General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models. IPDPS 2017: 244-253 - [c310]Mateo Valero:
Runtime Aware Architectures. IPDPS 2017: 819 - [c309]Pablo Fuentes, Enrique Vallejo, Ramón Beivide, Cyriel Minkenberg, Mateo Valero:
FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks. IPDPS 2017: 842-854 - [c308]Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi:
ATM: Approximate Task Memoization in the Runtime System. IPDPS 2017: 1140-1150 - [c307]Damian Roca, Daniel Nemirovsky, Marc Casas, Miquel Moretó, Mateo Valero, Mario Nemirovsky:
iQ: An Efficient and Flexible Queue-Based Simulation Framework. MASCOTS 2017: 143-149 - [c306]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems. SBAC-PAD 2017: 73-80 - 2016
- [j120]Roman Trobec, Radivoje Vasiljevic, Milo Tomasevic, Veljko Milutinovic, Ramón Beivide, Mateo Valero:
Interconnection Networks in Petascale Computer Systems: A Survey. ACM Comput. Surv. 49(3): 44:1-44:24 (2016) - [j119]Mariano Vázquez, Guillaume Houzeaux, Seid Koric, Antoni Artigues, Jazmin Aguado-Sierra, Ruth Aris, Daniel Mira, Hadrien Calmet, Fernando M. Cucchietti, Herbert Coppola-Owen, Ahmed Taha, Evan Dering Burness, José María Cela, Mateo Valero:
Alya: Multiphysics engineering simulation toward exascale. J. Comput. Sci. 14: 15-27 (2016) - [j118]Damian Roca, Daniel Nemirovsky, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero:
Emergent Behaviors in the Internet of Things: The Ultimate Ultra-Large-Scale System. IEEE Micro 36(6): 36-44 (2016) - [j117]Dimitrios Chasapis, Marc Casas, Miquel Moretó, Raul Vidal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite. ACM Trans. Archit. Code Optim. 12(4): 41:1-41:22 (2016) - [j116]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero:
Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Trans. Archit. Code Optim. 12(4): 60:1-60:26 (2016) - [j115]Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach. IEEE Trans. Computers 65(1): 256-269 (2016) - [j114]Pablo Fuentes, Enrique Vallejo, Cristobal Camarero, Ramón Beivide, Mateo Valero:
Network unfairness in dragonfly topologies. J. Supercomput. 72(12): 4468-4496 (2016) - [j113]Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. ACM Trans. Design Autom. Electr. Syst. 22(1): 16:1-16:26 (2016) - [c305]Paul Caheny, Marc Casas, Miquel Moretó, Hervé Gloaguen, Maxime Saintes, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling. PACT 2016: 275-286 - [c304]Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware. PACT 2016: 415-417 - [c303]Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core. PACT 2016: 447-448 - [c302]Mateo Valero:
Runtime Aware Architectures. DCNET 2016: 11-12 - [c301]Dimitrios Chasapis, Marc Casas, Miquel Moretó, Martin Schulz, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes. ICS 2016: 5:1-5:12 - [c300]Emilio Castillo, Miquel Moretó, Marc Casas, Lluc Alvarez, Enrique Vallejo, Kallia Chronaki, Rosa M. Badia, José Luis Bosque, Ramón Beivide, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
CATA: Criticality Aware Task Acceleration for Multicore Processors. IPDPS 2016: 413-422 - [c299]Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Future Vector Microprocessor Extensions for Data Aggregations. ISCA 2016: 418-430 - [c298]Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques. ISLPED 2016: 362-367 - [c297]Xubin Tan, Jaume Bosch, Daniel Jiménez-González, Carlos Álvarez-Martínez, Eduard Ayguadé, Mateo Valero:
Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models. ISPASS 2016: 225-234 - [c296]Mateo Valero:
Runtime Aware Architectures. PECCS 2016: 11 - [c295]Mateo Valero:
Runtime aware architectures. GPGPU@PPoPP 2016: 1 - [c294]Nikola Rajovic, Alejandro Rico, Filippo Mantovani, Daniel Ruiz, Josep Oriol Vilarrubi, Constantino Gómez, Luna Backes, Diego Nieto, Harald Servat, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Chris Adeniyi-Jones, Said Derradji, Hervé Gloaguen, Piero Lanucara, Nico Sanna, Jean-François Méhaut, Kevin Pouget, Brice Videau, Eric Boyer, Momme Allalen, Axel Auweter, David Brayford, Daniele Tafani, Volker Weinberg, Dirk Brömmel, René Halver, Jan H. Meinke, Ramón Beivide, Mariano Benito, Enrique Vallejo, Mateo Valero, Alex Ramírez:
The mont-blanc prototype: an alternative approach for HPC systems. SC 2016: 444-455 - [c293]Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó:
MUSA: a multi-level simulation approach for next-generation HPC machines. SC 2016: 526-537 - 2015
- [j112]Nikola Markovic, Daniel Nemirovsky, Osman S. Ünsal, Mateo Valero, Adrián Cristal:
Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core. IEEE Comput. Archit. Lett. 14(2): 160-163 (2015) - [j111]Fahimeh Yazdanpanah, Carlos Álvarez, Daniel Jiménez-González, Rosa M. Badia, Mateo Valero:
Picos: A hardware runtime architecture support for OmpSs. Future Gener. Comput. Syst. 53: 130-139 (2015) - [j110]Anton Kos, Saso Tomazic, Jakob Salom, Nemanja Trifunovic, Mateo Valero, Veljko Milutinovic:
New Benchmarking Methodology and Programming Model for Big Data Processing. Int. J. Distributed Sens. Networks 11: 271752:1-271752:7 (2015) - [j109]Nikola Markovic, Daniel Nemirovsky, Osman S. Unsal, Mateo Valero, Adrián Cristal:
Kernel-to-User-Mode Transition-Aware Hardware Scheduling. IEEE Micro 35(4): 37-47 (2015) - [j108]Daniel Nemirovsky, Nikola Markovic, Osman S. Unsal, Mateo Valero, Adrián Cristal:
Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model. IEEE Micro 35(5): 6-14 (2015) - [j107]Marina García, Enrique Vallejo, Ramón Beivide, Cristobal Camarero, Mateo Valero, Germán Rodríguez, Cyriel Minkenberg:
On-the-fly adaptive routing for dragonfly interconnection networks. J. Supercomput. 71(3): 1116-1142 (2015) - [c292]Lluc Alvarez, Miquel Moretó, Marc Casas, Emilio Castillo, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures. PACT 2015: 379-391 - [c291]Rubén Tous, Anastasios Gounaris, Carlos Tripiana, Jordi Torres, Sergi Girona, Eduard Ayguadé, Jesús Labarta, Yolanda Becerra, David Carrera, Mateo Valero:
Spark deployment and performance evaluation on the MareNostrum supercomputer. IEEE BigData 2015: 299-306 - [c290]Pablo Fuentes, Enrique Vallejo, Cristobal Camarero, Ramón Beivide, Mateo Valero:
Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns. CLUSTER 2015: 801-808 - [c289]Marc Casas, Miquel Moretó, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Aware Architectures. Euro-Par 2015: 16-27 - [c288]Nikola Markovic, Daniel Nemirovsky, Veljko Milutinovic, Osman S. Unsal, Mateo Valero, Adrián Cristal:
Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core. Euro-Par 2015: 122-134 - [c287]Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero:
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors. HPCA 2015: 26-38 - [c286]Víctor Jiménez, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Francisco J. Cazorla, Mateo Valero:
Increasing multicore system efficiency through intelligent bandwidth shifting. HPCA 2015: 39-50 - [c285]Kallia Chronaki, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures. ICS 2015: 329-338 - [c284]Pablo Fuentes, Enrique Vallejo, Marina García, Ramón Beivide, Germán Rodríguez, Cyriel Minkenberg, Mateo Valero:
Contention-Based Nonminimal Adaptive Routing in High-Radix Networks. IPDPS 2015: 103-112 - [c283]Lluc Alvarez, Lluís Vilanova, Miquel Moretó, Marc Casas, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Mateo Valero:
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. ISCA 2015: 720-732 - [c282]Ivan Ratkovic, Oscar Palomar, Milan Stanic, Milovan Duric, Djordje Peic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors. ISVLSI 2015: 19-26 - [c281]