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Mateo Valero

Mateo Valero Cortés

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affiliation: Polytechnic University of Catalonia, Barcelona, Spain
affiliation: Barcelona Supercomputing Center, Spain
award (2012): ACM Distinguished Service Award
award (2009): Harry H. Goode Memorial Award
award (2007): Eckert-Mauchly Award

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2020 – today

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2024
[c343]
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Julian Pavon, Iván Vargas Valdivieso, Carlos Rojas, César Hernández, Mehmet Aslan, Roger Figueras, Yichao Yuan, Joël Lindegger, Mohammed Alser, Francesc Moll, Santiago Marco-Sola, Oguz Ergin, Nishil Talati, Onur Mutlu, Osman S. Unsal, Mateo Valero, Adrián Cristal:
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms. ISCA 2024: 597-612
2023
[j139]
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Francesco Minervini, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal:
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. ACM Trans. Archit. Code Optim. 20(2): 28:1-28:25 (2023)
[c342]
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Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa:
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. DCIS 2023: 1-6
[c341]
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Julián Pavón, Iván Vargas Valdivieso, Joan Marimon, Roger Figueras, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal:
VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing. HPCA 2023: 1289-1302
2022
[c340]
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Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa:
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. DCIS 2022: 1-6
[c339]
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Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis A. Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal:
Adaptable Register File Organization for Vector Processors. HPCA 2022: 786-799
2021
[j138]
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Ulises Cortés, Eduardo Ulises Moya-Sánchez, Mateo Valero:
When Sally Met Harry or When AI Met HPC. Supercomput. Front. Innov. 8(1): 4-7 (2021)
[c338]
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Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero:
PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy. Euro-Par 2021: 599-615
[c337]
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Julian Pavon, Iván Vargas Valdivieso, Adrián Barredo, Joan Marimon, Miquel Moretó, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal:
VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations. HPCA 2021: 921-934
[c336]
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  - conf/meco/MilutinovicAYKD21
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Veljko M. Milutinovic, Erfan Sadeqi Azer, Kristy Yoshimoto, Gerhard Klimeck, Miljan Djordjevic, Milos Kotlar, Miroslav Bojovic, Bozidar Miladinovic, Nenad Korolija, Stevan Stankovic, Nenad Filipovic, Zoran Babovic, Miroslav Kosanic, Akira Tsuda, Mateo Valero, Massimo De Santo, Erich J. Neuhold, Jelena Skorucak, Laura Dipietro, Ivan Ratkovic:
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing. MECO 2021: 1-6
[i5]
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Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis Alfonso Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal:
Adaptable Register File Organization for Vector Processors. CoRR abs/2111.05301 (2021)
2020
[j137]
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Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero:
Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. Future Gener. Comput. Syst. 112: 832-847 (2020)
[j136]
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Damian Roca, Rodolfo A. Milito, Mario Nemirovsky, Mateo Valero:
Advances in the Hierarchical Emergent Behaviors (HEB) Approach to Autonomous Vehicles. IEEE Intell. Transp. Syst. Mag. 12(4): 57-65 (2020)
[j135]
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Adrián Barredo, Juan M. Cebrian, Mateo Valero, Marc Casas, Miquel Moretó:
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. J. Supercomput. 76(3): 1960-1979 (2020)
[j134]
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Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Using Arm's scalable vector extension on stencil codes. J. Supercomput. 76(3): 2039-2062 (2020)
[c335]
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Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luís Villa:
An Academic RISC-V Silicon Implementation Based on Open-Source Components. DCIS 2020: 1-6
[c334]
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Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. HPCA 2020: 717-728
[c333]
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Javier Ferrando, Juan Luis Domínguez, Jordi Torres, Raúl García, David García, Daniel Garrido, Jordi Cortada, Mateo Valero:
Improving Accuracy and Speeding Up Document Image Classification Through Parallel Systems. ICCS (2) 2020: 387-400
[c332]
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Vladimir Dimic, Miquel Moretó, Marc Casas, Jan Ciesko, Mateo Valero:
RICH: implementing reductions in the cache hierarchy. ICS 2020: 16:1-16:13
[c331]
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Luc Jaulmes, Miquel Moretó, Mateo Valero, Mattan Erez, Marc Casas:
Runtime-guided ECC protection using online estimation of memory vulnerability. SC 2020: 76
[i4]
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  - journals/corr/abs-2006-09141
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Javier Ferrando, Juan Luis Domínguez, Jordi Torres, Raúl García, David García, Daniel Garrido, Jordi Cortada, Mateo Valero:
Improving accuracy and speeding up Document Image Classification through parallel systems. CoRR abs/2006.09141 (2020)
[i3]
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  - journals/corr/abs-2009-10593
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Veljko Milutinovic, Milos Kotlar, Ivan Ratkovic, Nenad Korolija, Miljan Djordjevic, Kristy Yoshimoto, Erik Klem, Mateo Valero:
The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chips. CoRR abs/2009.10593 (2020)

2010 – 2019

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2019
[j133]
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Fabrizio Gagliardi, Miquel Moretó, Mauro Olivieri, Mateo Valero:
The international race towards Exascale in Europe. CCF Trans. High Perform. Comput. 1(1): 3-13 (2019)
[j132]
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Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero:
Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications. Int. J. Parallel Program. 47(3): 343-344 (2019)
[j131]
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Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Mateo Valero:
On the maturity of parallel applications for asymmetric multi-core processors. J. Parallel Distributed Comput. 127: 105-115 (2019)
[j130]
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Xubin Tan, Jaume Bosch, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero:
A Hardware Runtime for Task-Based Programming Models. IEEE Trans. Parallel Distributed Syst. 30(9): 1932-1946 (2019)
[c330]
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Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
POSTER: An Optimized Predication Execution for SIMD Extensions. PACT 2019: 479-480
[c329]
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Dimitrios Chasapis, Miquel Moretó, Martin Schulz, Barry Rountree, Mateo Valero, Marc Casas:
Power efficient job scheduling by predicting the impact of processor manufacturing variability. ICS 2019: 296-307
[c328]
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Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs. ICS 2019: 380-391
[c327]
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Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
A Vulnerability Factor for ECC-protected Memory. IOLTS 2019: 176-181
[c326]
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Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs: poster. PPoPP 2019: 415-416
2018
[j129]
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Daniel Nemirovsky, Tugberk Arkose, Nikola Markovic, Mario Nemirovsky, Osman S. Unsal, Adrián Cristal, Mateo Valero:
A General Guide to Applying Machine Learning to Computer Architecture. Supercomput. Front. Innov. 5(1): 95-115 (2018)
[j128]
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Helena Caminal, Diego Caballero, Juan M. Cebrian, Roger Ferrer, Marc Casas, Miquel Moretó, Xavier Martorell, Mateo Valero:
Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. J. Supercomput. 74(6): 2627-2637 (2018)
[j127]
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Paul Caheny, Lluc Alvarez, Said Derradji, Mateo Valero, Miquel Moretó, Marc Casas:
Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. IEEE Trans. Parallel Distributed Syst. 29(5): 1174-1187 (2018)
[j126]
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Luc Jaulmes, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers. IEEE Trans. Parallel Distributed Syst. 29(9): 1961-1974 (2018)
[j125]
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  - journals/tvlsi/RatkovicPSUCV18
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Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero:
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 639-652 (2018)
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Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Stencil codes on a vector length agnostic architecture. PACT 2018: 13:1-13:12
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Emilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Mateo Valero:
Architectural Support for Task Dependence Management with Flexible Software Scheduling. HPCA 2018: 283-295
[c323]
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Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies. ICS 2018: 207-217
[c322]
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Lluc Alvarez, Marc Casas, Jesús Labarta, Eduard Ayguadé, Mateo Valero, Miquel Moretó:
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs. ICS 2018: 218-228
[c321]
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Mateo Valero Cortés:
Runtime Aware Architectures. SIGSIM-PADS 2018: 3-4
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Isaac Sánchez Barrera, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Graph partitioning applied to DAG scheduling to reduce NUMA effects. PPoPP 2018: 419-420
[c319]
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Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moretó, Marc Casas:
Runtime-assisted cache coherence deactivation in task parallel programs. SC 2018: 35:1-35:12
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Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero:
Network and Parallel Computing - 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29 - December 1, 2018, Proceedings. Lecture Notes in Computer Science 11276, Springer 2018, ISBN 978-3-030-05676-6 [contents]
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Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
Memory Vulnerability: A Case for Delaying Error Reporting. CoRR abs/1810.06472 (2018)
2017
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Pablo Fuentes, Mariano Benito, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Andreea Anghel, Germán Rodríguez, Mitch Gusat, Cyriel Minkenberg, Mateo Valero:
A scalable synthetic traffic model of Graph500 for computer networks analysis. Concurr. Comput. Pract. Exp. 29(24) (2017)
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Vesna Smiljkovic, Osman S. Ünsal, Adrián Cristal, Mateo Valero:
Determinism at Standard-Library Level in TM-Based Applications. Int. J. Parallel Program. 45(1): 17-29 (2017)
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Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Adrián Cristal, Osman S. Unsal, Mateo Valero:
An Integrated Vector-Scalar Design on an In-Order ARM Core. ACM Trans. Archit. Code Optim. 14(2): 17:1-17:26 (2017)
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Kallia Chronaki, Alejandro Rico, Marc Casas, Miquel Moretó, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Task Scheduling Techniques for Asymmetric Multi-Core Systems. IEEE Trans. Parallel Distributed Syst. 28(7): 2074-2087 (2017)
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Daniel Nemirovsky, Tugberk Arkose, Nikola Markovic, Mario Nemirovsky, Osman S. Unsal, Adrián Cristal, Mateo Valero:
A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems. CARLA 2017: 3-20
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Mateo Valero:
Runtime Aware Architectures. Conf. Computing Frontiers 2017
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Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero:
Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals. Euro-Par 2017: 247-259
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Esteban Stafford, Borja Pérez, José Luis Bosque, Ramón Beivide, Mateo Valero:
To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy. Euro-Par 2017: 710-722
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Lluís Vilanova, Marc Jordà, Nacho Navarro, Yoav Etsion, Mateo Valero:
Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC. EuroSys 2017: 16-31
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Damian Roca, Josue V. Quiroga, Mateo Valero, Mario Nemirovsky:
Fog Function Virtualization: A flexible solution for IoT applications. FMEC 2017: 74-80
[c312]
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Xubin Tan, Jaume Bosch, Miquel Vidal, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero:
Picos, A Hardware Task-Dependence Manager for Task-Based Dataflow Programming Models. HPCS 2017: 878-880
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Xubin Tan, Jaume Bosch, Miquel Vidal, Carlos Álvarez, Daniel Jiménez-González, Eduard Ayguadé, Mateo Valero:
General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models. IPDPS 2017: 244-253
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Mateo Valero:
Runtime Aware Architectures. IPDPS 2017: 819
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Pablo Fuentes, Enrique Vallejo, Ramón Beivide, Cyriel Minkenberg, Mateo Valero:
FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks. IPDPS 2017: 842-854
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Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi:
ATM: Approximate Task Memoization in the Runtime System. IPDPS 2017: 1140-1150
[c307]
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Damian Roca, Daniel Nemirovsky, Marc Casas, Miquel Moretó, Mateo Valero, Mario Nemirovsky:
iQ: An Efficient and Flexible Queue-Based Simulation Framework. MASCOTS 2017: 143-149
[c306]
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Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems. SBAC-PAD 2017: 73-80
2016
[j120]
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Roman Trobec, Radivoje Vasiljevic, Milo Tomasevic, Veljko Milutinovic, Ramón Beivide, Mateo Valero:
Interconnection Networks in Petascale Computer Systems: A Survey. ACM Comput. Surv. 49(3): 44:1-44:24 (2016)
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Mariano Vázquez, Guillaume Houzeaux, Seid Koric, Antoni Artigues, Jazmin Aguado-Sierra, Ruth Aris, Daniel Mira, Hadrien Calmet, Fernando M. Cucchietti, Herbert Coppola-Owen, Ahmed Taha, Evan Dering Burness, José María Cela, Mateo Valero:
Alya: Multiphysics engineering simulation toward exascale. J. Comput. Sci. 14: 15-27 (2016)
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Damian Roca, Daniel Nemirovsky, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero:
Emergent Behaviors in the Internet of Things: The Ultimate Ultra-Large-Scale System. IEEE Micro 36(6): 36-44 (2016)
[j117]
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Dimitrios Chasapis, Marc Casas, Miquel Moretó, Raul Vidal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite. ACM Trans. Archit. Code Optim. 12(4): 41:1-41:22 (2016)
[j116]
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Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero:
Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Trans. Archit. Code Optim. 12(4): 60:1-60:26 (2016)
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Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach. IEEE Trans. Computers 65(1): 256-269 (2016)
[j114]
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Pablo Fuentes, Enrique Vallejo, Cristobal Camarero, Ramón Beivide, Mateo Valero:
Network unfairness in dragonfly topologies. J. Supercomput. 72(12): 4468-4496 (2016)
[j113]
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Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. ACM Trans. Design Autom. Electr. Syst. 22(1): 16:1-16:26 (2016)
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Paul Caheny, Marc Casas, Miquel Moretó, Hervé Gloaguen, Maxime Saintes, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling. PACT 2016: 275-286
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Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware. PACT 2016: 415-417
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Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core. PACT 2016: 447-448
[c302]
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Mateo Valero:
Runtime Aware Architectures. DCNET 2016: 11-12
[c301]
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Dimitrios Chasapis, Marc Casas, Miquel Moretó, Martin Schulz, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes. ICS 2016: 5:1-5:12
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Emilio Castillo, Miquel Moretó, Marc Casas, Lluc Alvarez, Enrique Vallejo, Kallia Chronaki, Rosa M. Badia, José Luis Bosque, Ramón Beivide, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
CATA: Criticality Aware Task Acceleration for Multicore Processors. IPDPS 2016: 413-422
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Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Future Vector Microprocessor Extensions for Data Aggregations. ISCA 2016: 418-430
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Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques. ISLPED 2016: 362-367
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Xubin Tan, Jaume Bosch, Daniel Jiménez-González, Carlos Álvarez-Martínez, Eduard Ayguadé, Mateo Valero:
Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models. ISPASS 2016: 225-234
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Mateo Valero:
Runtime Aware Architectures. PECCS 2016: 11
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Mateo Valero:
Runtime aware architectures. GPGPU@PPoPP 2016: 1
[c294]
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Nikola Rajovic, Alejandro Rico, Filippo Mantovani, Daniel Ruiz, Josep Oriol Vilarrubi, Constantino Gómez, Luna Backes, Diego Nieto, Harald Servat, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Chris Adeniyi-Jones, Said Derradji, Hervé Gloaguen, Piero Lanucara, Nico Sanna, Jean-François Méhaut, Kevin Pouget, Brice Videau, Eric Boyer, Momme Allalen, Axel Auweter, David Brayford, Daniele Tafani, Volker Weinberg, Dirk Brömmel, René Halver, Jan H. Meinke, Ramón Beivide, Mariano Benito, Enrique Vallejo, Mateo Valero, Alex Ramírez:
The mont-blanc prototype: an alternative approach for HPC systems. SC 2016: 444-455
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Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó:
MUSA: a multi-level simulation approach for next-generation HPC machines. SC 2016: 526-537
2015
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Nikola Markovic, Daniel Nemirovsky, Osman S. Ünsal, Mateo Valero, Adrián Cristal:
Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core. IEEE Comput. Archit. Lett. 14(2): 160-163 (2015)
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Fahimeh Yazdanpanah, Carlos Álvarez, Daniel Jiménez-González, Rosa M. Badia, Mateo Valero:
Picos: A hardware runtime architecture support for OmpSs. Future Gener. Comput. Syst. 53: 130-139 (2015)
[j110]
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Anton Kos, Saso Tomazic, Jakob Salom, Nemanja Trifunovic, Mateo Valero, Veljko Milutinovic:
New Benchmarking Methodology and Programming Model for Big Data Processing. Int. J. Distributed Sens. Networks 11: 271752:1-271752:7 (2015)
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Nikola Markovic, Daniel Nemirovsky, Osman S. Unsal, Mateo Valero, Adrián Cristal:
Kernel-to-User-Mode Transition-Aware Hardware Scheduling. IEEE Micro 35(4): 37-47 (2015)
[j108]
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Daniel Nemirovsky, Nikola Markovic, Osman S. Unsal, Mateo Valero, Adrián Cristal:
Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model. IEEE Micro 35(5): 6-14 (2015)
[j107]
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Marina García, Enrique Vallejo, Ramón Beivide, Cristobal Camarero, Mateo Valero, Germán Rodríguez, Cyriel Minkenberg:
On-the-fly adaptive routing for dragonfly interconnection networks. J. Supercomput. 71(3): 1116-1142 (2015)
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Lluc Alvarez, Miquel Moretó, Marc Casas, Emilio Castillo, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures. PACT 2015: 379-391
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Rubén Tous, Anastasios Gounaris, Carlos Tripiana, Jordi Torres, Sergi Girona, Eduard Ayguadé, Jesús Labarta, Yolanda Becerra, David Carrera, Mateo Valero:
Spark deployment and performance evaluation on the MareNostrum supercomputer. IEEE BigData 2015: 299-306
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Pablo Fuentes, Enrique Vallejo, Cristobal Camarero, Ramón Beivide, Mateo Valero:
Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns. CLUSTER 2015: 801-808
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Marc Casas, Miquel Moretó, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Aware Architectures. Euro-Par 2015: 16-27
[c288]
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Nikola Markovic, Daniel Nemirovsky, Veljko Milutinovic, Osman S. Unsal, Mateo Valero, Adrián Cristal:
Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core. Euro-Par 2015: 122-134
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Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero:
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors. HPCA 2015: 26-38
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Víctor Jiménez, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Francisco J. Cazorla, Mateo Valero:
Increasing multicore system efficiency through intelligent bandwidth shifting. HPCA 2015: 39-50
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Kallia Chronaki, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures. ICS 2015: 329-338
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Pablo Fuentes, Enrique Vallejo, Marina García, Ramón Beivide, Germán Rodríguez, Cyriel Minkenberg, Mateo Valero:
Contention-Based Nonminimal Adaptive Routing in High-Radix Networks. IPDPS 2015: 103-112
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Lluc Alvarez, Lluís Vilanova, Miquel Moretó, Marc Casas, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Mateo Valero:
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. ISCA 2015: 720-732
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Ivan Ratkovic, Oscar Palomar, Milan Stanic, Milovan Duric, Djordje Peic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors. ISVLSI 2015: 19-26
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Raul Vidal, Marc Casas, Miquel Moretó, Dimitrios Chasapis, Roger Ferrer, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads. IWOMP 2015: 60-72
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Milovan Duric, Milan Stanic, Ivan Ratkovic, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero, Aaron Smith:
Imposing coarse-grained reconfiguration to general purpose processors. SAMOS 2015: 42-51
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Nikola Markovic, Daniel Nemirovsky, Osman S. Unsal, Mateo Valero, Adrián Cristal:
Performance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs. SBAC-PAD 2015: 33-40
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Luc Jaulmes, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Exploiting asynchrony from exact forward recovery for DUE in iterative solvers. SC 2015: 53:1-53:12
[i1]
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David Prat, Cristobal Ortega, Marc Casas, Miquel Moretó, Mateo Valero:
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7. CoRR abs/1501.02282 (2015)
2014
[j106]
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Qixiao Liu, Víctor Jiménez, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Per-task Energy Accounting in Computing Systems. IEEE Comput. Archit. Lett. 13(2): 85-88 (2014)
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Mateo Valero, Ulises Cortés:
Editorial. Computación y Sistemas 18(4) (2014)
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Sasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators. Int. J. Parallel Program. 42(1): 119-139 (2014)
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Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahulkumar Gayatri, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Joshua Landwehr, Nhat Minh Lê, Feng Li, Mikel Luján, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stéphane Zuckerman, Mateo Valero:
TERAFLUX: Harnessing dataflow in next generation teradevices. Microprocess. Microsystems 38(8): 976-990 (2014)
[j102]
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Mateo Valero, Miquel Moretó, Marc Casas, Eduard Ayguadé, Jesús Labarta:
Runtime-Aware Architectures: A First Approach. Supercomput. Front. Innov. 1(1): 29-44 (2014)
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Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation. ACM Trans. Design Autom. Electr. Syst. 20(1): 10:1-10:25 (2014)
[j100]
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Bojan Maric, Jaume Abella, Mateo Valero:
Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2211-2215 (2014)
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Tassadaq Hussain, Oscar Palomar, Osman S. Ünsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Amna Haider:
Stand-Alone Memory Controller for Graphics System. ARC 2014: 108-120
[c276]
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Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero:
PVMC: Programmable Vector Memory Controller. ASAP 2014: 240-247
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Pablo Fuentes, José Luis Bosque, Ramón Beivide, Mateo Valero, Cyriel Minkenberg:
Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster. BDC 2014: 83-89
[c274]
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Srdan Stipic, Vasileios Karakostas, Vesna Smiljkovic, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Dynamic transaction coalescing. Conf. Computing Frontiers 2014: 18:1-18:10
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Milovan Duric, Oscar Palomar, Aaron Smith, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger:
EVX: Vector execution on low power EDGE cores. DATE 2014: 1-4
[c272]
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Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
DReAM: Per-Task DRAM Energy Metering in Multicore Systems. Euro-Par 2014: 111-123
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Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Santhosh Kumar Rethinagiri:
APMC: advanced pattern based memory controller (abstract only). FPGA 2014: 252
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Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero:
MAPC: Memory access pattern based controller. FPL 2014: 1-4
[c269]
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Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal:
AMMC: Advanced Multi-Core Memory Controller. FPT 2014: 292-295
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Milan Stanic, Oscar Palomar, Ivan Ratkovic, Milovan Duric, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi. HPCS 2014: 47-54
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Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero:
Advanced Pattern based Memory Controller for FPGA based HPC applications. HPCS 2014: 287-294
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Alex Ramírez, Ayose Falcón, Oliverio J. Santana, Mateo Valero:
Author retrospective for software trace cache. ICS 25th Anniversary 2014: 45-47
[c265]
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Anton Kos, Sao Tomac Jakob, Nemanja Trifunovic, Mateo Valero, Veljko Milutinovic:
Big Data Processing: Data Flow vs Control Flow (New Benchmarking Methodology). IIKI 2014: 56-59
[c264]
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Alessandro Morari, Antonino Tumeo, Daniel G. Chavarría-Miranda, Oreste Villa, Mateo Valero:
Scaling Irregular Applications through Data Aggregation and Software Multithreading. IPDPS 2014: 1126-1135
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Ivan Tanasic, Isaac Gelado, Javier Cabezas, Alex Ramírez, Nacho Navarro, Mateo Valero:
Enabling preemptive multiprogramming on GPUs. ISCA 2014: 193-204
[c262]
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Lluís Vilanova, Muli Ben-Yehuda, Nacho Navarro, Yoav Etsion, Mateo Valero:
CODOMs: Protecting software with Code-centric memory Domains. ISCA 2014: 469-480
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Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders. ISVLSI 2014: 118-123
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Tassadaq Hussain, Nehir Sönmez, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal:
PAMS: Pattern Aware Memory System for embedded systems. ReConFig 2014: 1-7
[c259]
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Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero, Doug Burger, Alexander V. Veidenbaum:
Dynamic-vector execution on a general purpose EDGE chip multiprocessor. ICSAMOS 2014: 18-25
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Vesna Smiljkovic, Srdan Stipic, Christof Fetzer, Osman S. Unsal, Adrián Cristal, Mateo Valero:
DeTrans: Deterministic and Parallel execution of Transactions. SBAC-PAD 2014: 152-159
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Vladimir Subotic, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Automatic Exploration of Potential Parallelism in Sequential Applications. ISC 2014: 156-171
2013
[j99]
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Michael J. Flynn, Oskar Mencer, Veljko M. Milutinovic, Goran Rakocevic, Per Stenström, Roman Trobec, Mateo Valero:
Moving from petaflops to petadata. Commun. ACM 56(5): 39-42 (2013)
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Vladimir Subotic, Steffen Brinkmann, Vladimir Marjanovic, Rosa M. Badia, José Gracia, Christoph Niethammer, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Programmability and portability for exascale: Top down programming methodology and tools with StarSs. J. Comput. Sci. 4(6): 450-456 (2013)
[j97]
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Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Mateo Valero:
Fair CPU time accounting in CMP+SMT processors. ACM Trans. Archit. Code Optim. 9(4): 50:1-50:25 (2013)
[j96]
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Qixiao Liu, Miquel Moretó, Víctor Jiménez, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hardware support for accurate per-task energy metering in multicore systems. ACM Trans. Archit. Code Optim. 10(4): 34:1-34:27 (2013)
[j95]
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Srdan Stipic, Vesna Smiljkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Profile-guided transaction coalescing - lowering transactional overheads by merging transactions. ACM Trans. Archit. Code Optim. 10(4): 50:1-50:18 (2013)
[j94]
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Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Trans. Computers 62(4): 813-826 (2013)
[j93]
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Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors. IEEE Trans. Parallel Distributed Syst. 24(12): 2513-2525 (2013)
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Mateo Valero:
Killer-mobiles: The way towards energy efficient high performance computers? ACSD 2013
[c255]
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Bojan Maric, Jaume Abella, Mateo Valero:
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation. DAC 2013: 84:1-84:8
[c254]
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Bojan Maric, Jaume Abella, Mateo Valero:
Efficient cache architectures for reliable hybrid voltage operation using EDC codes. DATE 2013: 917-920
[c253]
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Marco Solinas, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Luján, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stéphane Zuckerman, Roberto Giorgi:
The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. DSD 2013: 272-279
[c252]
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Marina García, Enrique Vallejo, Ramón Beivide, Miguel Odriozola, Cristobal Camarero, Mateo Valero, Jesús Labarta, Germán Rodríguez:
Global misrouting policies in two-level hierarchical networks. INA-OCMC@HiPEAC 2013: 13-16
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Marina García, Enrique Vallejo, Ramón Beivide, Mateo Valero, Germán Rodríguez:
OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management. Hot Interconnects 2013: 55-62
[c250]
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Sasa Tomic, Ege Akpinar, Adrián Cristal, Osman S. Unsal, Mateo Valero:
EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory. ICCS 2013: 270-279
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Marina García, Enrique Vallejo, Ramón Beivide, Miguel Odriozola, Mateo Valero:
Efficient Routing Mechanisms for Dragonfly Networks. ICPP 2013: 582-592
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Franck Cappello, Wolfgang Gentzsch, Mateo Valero, Mads Nygård:
HPCS 2013 panel: The era of exascale sciences: Challenges, needs and requirements. HPCS 2013
[c247]
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Vesna Smiljkovic, Martin Nowack, Neboja Miletic, Tim Harris, Osman S. Ünsal, Adrián Cristal, Mateo Valero:
TM-dietlibc: A TM-aware Real-World System Library. IPDPS 2013: 1266-1274
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Alessandro Morari, Mateo Valero:
HPC System Software for Regular and Irregular Parallel Applications. IPDPS Workshops 2013: 2242-2245
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Alejandro Rico, Alex Ramírez, Mateo Valero:
Trace filtering of multithreaded applications for CMP memory simulation. ISPASS 2013: 134-135
[c244]
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Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
On the selection of adder unit in energy efficient vector processing. ISQED 2013: 143-150
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Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero:
Identifying Critical Code Sections in Dataflow Programming Models. PDP 2013: 29-37
[c242]
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Mateo Valero:
Killer-mobiles - The Way Towards Energy Efficient High Performance Computers? PECCS 2013
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Nikola Rajovic, Paul M. Carpenter, Isaac Gelado, Nikola Puzovic, Alex Ramírez, Mateo Valero:
Supercomputing with commodity CPUs: are mobile SoCs ready for HPC? SC 2013: 40:1-40:12
2012
[j92]
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Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
Profiling and Optimizing Transactional Memory Applications. Int. J. Parallel Program. 40(1): 25-56 (2012)
[j91]
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Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache. Integr. 45(3): 237-245 (2012)
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Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero:
Understanding the future of energy-performance trade-off via DVFS in HPC environments. J. Parallel Distributed Comput. 72(4): 579-590 (2012)
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Oriol Arcas, Nehir Sönmez, Gokhan Sayilar, Satnam Singh, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
Resource-bounded multicore emulation using Beefarm. Microprocess. Microsystems 36(8): 620-631 (2012)
[j88]
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Javier Verdú, Alex Pajuelo, Mateo Valero:
The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications. IEEE Micro 32(6): 17-27 (2012)
[j87]
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Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero:
Parallel job scheduling for power constrained HPC systems. Parallel Comput. 38(12): 615-630 (2012)
[j86]
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J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. 8(4): 31:1-31:20 (2012)
[j85]
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Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramírez, Mateo Valero:
On the simulation of large-scale architectures using multiple application abstraction levels. ACM Trans. Archit. Code Optim. 8(4): 36:1-36:20 (2012)
[j84]
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Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
CPU Accounting for Multicore Processors. IEEE Trans. Computers 61(2): 251-264 (2012)
[j83]
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Carlos Álvarez, Jesús Corbal, Mateo Valero:
Dynamic Tolerance Region Computing for Multimedia. IEEE Trans. Computers 61(5): 650-665 (2012)
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Petar Radojkovic, Vladimir Cakarevic, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Optimal task assignment in multithreaded processors: a statistical approach. ASPLOS 2012: 235-248
[c239]
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Srdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrián Cristal, Osman S. Ünsal, Mateo Valero:
TagTM - accelerating STMs with hardware tags for fast meta-data access. DATE 2012: 39-44
[c238]
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Bojan Maric, Jaume Abella, Mateo Valero:
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. ACM Great Lakes Symposium on VLSI 2012: 245-250
[c237]
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Marina García, Enrique Vallejo, Ramón Beivide, Miguel Odriozola, Cristobal Camarero, Mateo Valero, Germán Rodríguez, Jesús Labarta, Cyriel Minkenberg:
On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks. ICPP 2012: 279-288
[c236]
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Gokcen Kestor, Roberto Gioiosa, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Enhancing the performance of assisted execution runtime systems through hardware/software techniques. ICS 2012: 153-162
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Alessandro Morari, Roberto Gioiosa, Robert W. Wisniewski, Bryan S. Rosenburg, Todd Inglett, Mateo Valero:
Evaluating the Impact of TLB Misses on Future HPC Systems. IPDPS 2012: 1010-1021
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Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Vector Extensions for Decision Support DBMS Acceleration. MICRO 2012: 166-176
[c233]
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Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum:
Improving Cache Management Policies Using Dynamic Reuse Distances. MICRO 2012: 389-400
[c232]
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Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Novel SRAM bias control circuits for a low power L1 data cache. NORCHIP 2012: 1-6
[c231]
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Germán Rodríguez, Cyriel Minkenberg, Ronald P. Luijten, Ramón Beivide, Patrick Geoffray, Jesús Labarta, Mateo Valero, Steve Poole:
The Network Adapter: The Missing Link between MPI Applications and Network Performance. SBAC-PAD 2012: 1-8
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Alessandro Morari, Antonino Tumeo, Oreste Villa, Simone Secchi, Mateo Valero:
Efficient Sorting on the Tilera Manycore Architecture. SBAC-PAD 2012: 171-178
2011
[j82]
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Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero:
Scalable multicore architectures for long DNA sequence comparison. Concurr. Comput. Pract. Exp. 23(17): 2205-2219 (2011)
[j81]
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Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Characterizing Power and Temperature Behavior of POWER6-Based System. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 228-241 (2011)
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Jack J. Dongarra, Peter H. Beckman, Terry Moore, Patrick Aerts, Giovanni Aloisio, Jean-Claude Andre, David Barkai, Jean-Yves Berthou, Taisuke Boku, Bertrand Braunschweig, Franck Cappello, Barbara M. Chapman, Xuebin Chi, Alok N. Choudhary, Sudip S. Dosanjh, Thom H. Dunning, Sandro Fiore, Al Geist, Bill Gropp, Robert J. Harrison, Mark Hereld, Michael A. Heroux, Adolfy Hoisie, Koh Hotta, Zhong Jin, Yutaka Ishikawa, Fred Johnson, Sanjay Kale, Richard Kenway, David E. Keyes, Bill Kramer, Jesús Labarta, Alain Lichnewsky, Thomas Lippert, Bob Lucas, Barney Maccabe, Satoshi Matsuoka, Paul Messina, Peter Michielse, Bernd Mohr, Matthias S. Müller, Wolfgang E. Nagel, Hiroshi Nakashima, Michael E. Papka, Daniel A. Reed, Mitsuhisa Sato, Edward Seidel, John Shalf, David Skinner, Marc Snir, Thomas L. Sterling, Rick Stevens, Frederick H. Streitz, Bob Sugar, Shinji Sumimoto, William M. Tang, John A. Taylor, Rajeev Thakur, Anne E. Trefethen, Mateo Valero, Aad J. van der Steen, Jeffrey S. Vetter, Peg Williams, Robert W. Wisniewski, Katherine A. Yelick:
The International Exascale Software Project roadmap. Int. J. High Perform. Comput. Appl. 25(1): 3-60 (2011)
[j79]
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Enrique Vallejo, Sutirtha Sanyal, Tim Harris, Fernando Vallejo, Ramón Beivide, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Hybrid Transactional Memory with Pessimistic Concurrency Control. Int. J. Parallel Program. 39(3): 375-396 (2011)
[j78]
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Juan Gonzalez, Judit Giménez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero:
Simulating Whole Supercomputer Applications. IEEE Micro 31(3): 32-45 (2011)
[j77]
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Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities. IEEE Micro 31(3): 60-71 (2011)
[j76]
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Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems. SIGBED Rev. 8(3): 32-35 (2011)
[j75]
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Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only). SIGMETRICS Perform. Evaluation Rev. 39(3): 19 (2011)
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Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Dynamic Cache Partitioning Based on the MLP of Cache Misses. Trans. High Perform. Embed. Archit. Compil. 3: 3-23 (2011)
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Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero:
A Highly Scalable Parallel Implementation of H.264. Trans. High Perform. Embed. Archit. Compil. 4: 111-134 (2011)
[j72]
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Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericàs, Félix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguadé, José María Cela, Mateo Valero:
Assessing Accelerator-Based HPC Reverse Time Migration. IEEE Trans. Parallel Distributed Syst. 22(1): 147-162 (2011)
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Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory. PACT 2011: 199-200
[c228]
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Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems. PACT 2011: 221-231
[c227]
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Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT 2011: 361-371
[c226]
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Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero:
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. ARC 2011: 350-362
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Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid high-performance low-power and ultra-low energy reliable caches. Conf. Computing Frontiers 2011: 12
[c224]
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Vladimir Subotic, Roger Ferrer, José Carlos Sancho, Jesús Labarta, Mateo Valero:
Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications. Euro-Par (1) 2011: 39-51
[c223]
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Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero:
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. FCCM 2011: 146-153
[c222]
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Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330
[c221]
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Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero:
RVC: a mechanism for time-analyzable real-time processors with faulty caches. HiPEAC 2011: 97-106
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Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Mateo Valero:
FIMSIM: A fault injection infrastructure for microarchitectural simulators. ICCD 2011: 431-432
[c219]
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Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero:
Linear programming based parallel job scheduling for power constrained systems. HPCS 2011: 72-80
[c218]
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Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides:
RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 2011: 25-30
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Alessandro Morari, Roberto Gioiosa, Robert W. Wisniewski, Francisco J. Cazorla, Mateo Valero:
A Quantitative Analysis of OS Noise. IPDPS 2011: 852-863
[c216]
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Alejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramírez, Mateo Valero:
Trace-driven simulation of multithreaded applications. ISPASS 2011: 87-96
[c215]
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Ruken Zilan, Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero:
An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures. MASCOTS 2011: 478-481
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Jesús Labarta, Vladimir Marjanovic, Eduard Ayguadé, Rosa M. Badia, Mateo Valero:
Hybrid Parallel Programming with MPI/StarSs. PARCO 2011: 621-628
[c213]
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Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero:
The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap. PDP 2011: 191-198
[c212]
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Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Robert I. Davis, Mateo Valero:
IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2011: 280-290
[c211]
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Augusto Vega, Felipe Cabarcas, Alex Ramírez, Mateo Valero:
Breaking the bandwidth wall in chip multiprocessors. ICSAMOS 2011: 255-262
[c210]
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  - conf/sbac-pad/TomicCUV11
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Sasa Tomic, Adrián Cristal, Osman S. Ünsal, Mateo Valero:
Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing. SBAC-PAD 2011: 80-87
[c209]
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Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
RMS-TM: a comprehensive benchmark suite for transactional memory systems. ICPE 2011: 335-346
2010
[j71]
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Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero:
Utilization driven power-aware parallel job scheduling. Comput. Sci. Res. Dev. 25(3-4): 207-216 (2010)
[j70]
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Mateo Valero, Nacho Navarro:
Multicore: The View from Europe. IEEE Micro 30(5): 2-4 (2010)
[j69]
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Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero:
On the Problem of Evaluating the Performance of Multiprogrammed Workloads. IEEE Trans. Computers 59(12): 1722-1728 (2010)
[c208]
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Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Power and thermal characterization of POWER6 system. PACT 2010: 7-18
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Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
Discovering and understanding performance bottlenecks in transactional applications. PACT 2010: 285-294
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero:
Efficient runahead threads. PACT 2010: 443-452
[c205]
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Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo Valero:
Exploiting Inactive Rename Slots for Detecting Soft Errors. ARCS 2010: 126-137
[c204]
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Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero:
Load balancing using dynamic cache allocation. Conf. Computing Frontiers 2010: 153-164
[c203]
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  - conf/cisis/IsazaSGRV10
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Sebastián Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero:
Scalability Analysis of Progressive Alignment on a Multicore. CISIS 2010: 889-894
[c202]
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Roberto Gioiosa, Sally A. McKee, Mateo Valero:
Designing OS for HPC Applications: Scheduling. CLUSTER 2010: 78-87
[c201]
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Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero:
A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications. CLUSTER 2010: 275-283
[c200]
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Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero:
Long DNA Sequence Comparison on Multicore Architectures. Euro-Par (2) 2010: 247-259
[c199]
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Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero:
Optimizing job performance under a given power constraint in HPC centers. Green Computing Conference 2010: 257-267
[c198]
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Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Overlapping communication and computation by using a hybrid MPI/SMPSs approach. ICS 2010: 5-16
[c197]
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Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
Power and performance aware reconfigurable cache for CMPs. IFMT 2010: 1:1-1:12
[c196]
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Augusto Vega, Alejandro Rico, Felipe Cabarcas, Alex Ramírez, Mateo Valero:
Comparing last-level cache designs for CMP architectures. IFMT 2010: 2:1-2:11
[c195]
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Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero:
BSLD threshold driven power management policy for HPC centers. IPDPS Workshops 2010: 1-8
[c194]
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Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero:
Adapting cache partitioning algorithms to pseudo-LRU replacement policies. IPDPS 2010: 1-12
[c193]
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Vladimir Subotic, Jesús Labarta, Mateo Valero:
Simulation environment for studying overlap of communication and computation. ISPASS 2010: 115-116
[c192]
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  - conf/micro/EtsionCRRBALV10
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Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Task Superscalar: An Out-of-Order Task Pipeline. MICRO 2010: 89-100
[c191]
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Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero:
Architectural Support for Fair Reader-Writer Locking. MICRO 2010: 275-286
[c190]
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Ferad Zyulkyarov, Tim Harris, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Debugging programs that use atomic blocks and transactional memory. PPoPP 2010: 57-66
[c189]
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  - conf/ppopp/RadojkovicCVPCNV10
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Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Thread to strand binding of parallel network applications in massive multi-threaded systems. PPoPP 2010: 191-202
[c188]
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Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Effective communication and computation overlap with hybrid MPI/SMPSs. PPoPP 2010: 337-338
[c187]
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Víctor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
Trends and techniques for energy efficient architectures. VLSI-SoC 2010: 276-279

2000 – 2009

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What is the meaning of the colors in the publication lists?

2009
[j68]
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Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
CPU Accounting in CMP Processors. IEEE Comput. Archit. Lett. 8(1): 17-20 (2009)
[j67]
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Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero:
An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embed. Syst. Lett. 1(4): 86-90 (2009)
[j66]
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Jack J. Dongarra, Peter H. Beckman, Patrick Aerts, Franck Cappello, Thomas Lippert, Satoshi Matsuoka, Paul Messina, Terry Moore, Rick Stevens, Anne E. Trefethen, Mateo Valero:
The International Exascale Software Project: a Call To Cooperative Action By the Global High-Performance Community. Int. J. High Perform. Comput. Appl. 23(4): 309-322 (2009)
[j65]
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Jesús Labarta, Eduard Ayguadé, Mateo Valero:
BSC Vision Towards Exascale. Int. J. High Perform. Comput. Appl. 23(4): 340-343 (2009)
[j64]
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  - journals/rasi/AlvarezRVAM09
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Mauricio Alvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck:
Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA. Rev. Avances en Sistemas Informática 6(1): 219-228 (2009)
[j63]
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Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero:
FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Oper. Syst. Rev. 43(2): 86-96 (2009)
[j62]
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Alejandro Rico, Alex Ramírez, Mateo Valero:
Available task-level parallelism on the Cell BE. Sci. Program. 17(1-2): 59-76 (2009)
[j61]
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  - journals/tc/SantanaFRV09
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Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero:
DIA: A Complexity-Effective Decoding Architecture. IEEE Trans. Computers 58(4): 448-462 (2009)
[c186]
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Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. PACT 2009: 203-213
[c185]
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Friman Sánchez, Alex Ramírez, Mateo Valero:
Quantitative analysis of sequence alignment applications on multiprocessor architectures. Conf. Computing Frontiers 2009: 61-70
[c184]
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  - conf/cluster/RodriguezMBLLV09
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Germán Rodríguez, Cyriel Minkenberg, Ramón Beivide, Ronald P. Luijten, Jesús Labarta, Mateo Valero:
Oblivious routing schemes in extended generalized Fat Tree networks. CLUSTER 2009: 1-8
[c183]
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  - conf/hpcc/SanyalRCUV09
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Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory. HPCC 2009: 171-179
[c182]
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Mauricio Alvarez-Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero:
Scalability of Macroblock-level Parallelism for H.264 Decoding. ICPADS 2009: 236-243
[c181]
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Code Semantic-Aware Runahead Threads. ICPP 2009: 437-444
[c180]
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Mateo Valero:
A european perspective on supercomputing. ICS 2009: 1
[c179]
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Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero:
QuakeTM: parallelizing a complex sequential application using transactional memory. ICS 2009: 126-135
[c178]
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Germán Rodríguez, Ramón Beivide, Cyriel Minkenberg, Jesús Labarta, Mateo Valero:
Exploring pattern-aware routing in generalized fat tree networks. ICS 2009: 276-285
[c177]
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Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum:
Power-aware load balancing of large scale MPI applications. IPDPS 2009: 1-8
[c176]
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Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Clock gate on abort: Towards energy-efficient hardware Transactional Memory. IPDPS 2009: 1-8
[c175]
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Nehir Sönmez, Tim Harris, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. IPDPS 2009: 1-10
[c174]
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Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero:
Hardware support for WCET analysis of hard real-time multicore systems. ISCA 2009: 57-68
[c173]
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Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero:
EazyHTM: eager-lazy hardware transactional memory. MICRO 2009: 145-155
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Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Characterizing the resource-sharing levels in the UltraSPARC T2 processor. MICRO 2009: 481-492
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Ferad Zyulkyarov, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero:
Atomic quake: using transactional memory in an interactive multiplayer game server. PPoPP 2009: 25-34
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Chinmay Eishan Kulkarni, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero:
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. PPoPP 2009: 307-308
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Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Thread to Core Assignment in SMT On-Chip Multiprocessors. SBAC-PAD 2009: 67-74
2008
[j60]
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Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Power-efficient VLIW design using clustering and widening. Int. J. Embed. Syst. 3(3): 141-149 (2008)
[j59]
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Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero:
Nebelung: Execution Environment for Transactional OpenMP. Int. J. Parallel Program. 36(3): 326-346 (2008)
[j58]
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Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith:
Multicore Resource Management. IEEE Micro 28(3): 6-16 (2008)
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Javier Verdú, Mario Nemirovsky, Mateo Valero:
MultiLayer processing - an execution model for parallel stateful packet processing. ANCS 2008: 79-88
[c167]
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Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero:
Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. ARCS 2008: 173-187
[c166]
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Pedro Ángel Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luis Jiménez Laredo, Sally A. McKee:
Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation 2008: 1941-1948
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Cristian Perfumo, Nehir Sönmez, Srdjan Stipic, Osman S. Unsal, Adrián Cristal, Tim Harris, Mateo Valero:
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Conf. Computing Frontiers 2008: 67-78
[c164]
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Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luis Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee:
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. EvoWorkshops 2008: 175-183
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Mateo Valero, Jesús Labarta:
Supercomputing for the Future, Supercomputing from the Past (Keynote). HiPEAC 2008: 3-5
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Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero:
LPA: A First Approach to the Loop Processor Architecture. HiPEAC 2008: 273-287
[c161]
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Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352
[c160]
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Runahead Threads to improve SMT performance. HPCA 2008: 149-158
[c159]
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Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. ICPP 2008: 173-181
[c158]
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Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero:
Balancing HPC applications through smart allocation of resources in MT processors. IPDPS 2008: 1-12
[c157]
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Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero:
A Two-Level Load/Store Queue Based on Execution Locality. ISCA 2008: 25-36
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Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426
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Ferad Zyulkyarov, Adrián Cristal, Sanja Cvijic, Eduard Ayguadé, Mateo Valero, Osman S. Unsal, Tim Harris:
WormBench: a configurable workload for evaluating transactional memory systems. MEDEA@PACT 2008: 61-68
[c154]
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Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero:
A distributed processor state management architecture for large-window processors. MICRO 2008: 11-22
[c153]
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Sebastián Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero:
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. SAMOS 2008: 53-64
[c152]
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Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero:
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD 2008: 63-70
[c151]
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Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Measuring Operating System Overhead on CMT Processors. SBAC-PAD 2008: 133-140
[c150]
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Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero:
A dynamic scheduler for balancing HPC applications. SC 2008: 41
[c149]
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Miquel Pericàs, Ricardo Chaves, Georgi Gaydadjiev, Stamatis Vassiliadis, Mateo Valero:
Vectorized AES Core for High-throughput Secure Environments. VECPAR 2008: 83-94
2007
[j57]
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Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Explaining Dynamic Cache Partitioning Speed Ups. IEEE Comput. Archit. Lett. 6(1): 1-4 (2007)
[j56]
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Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero:
Transactional Memory: An Overview. IEEE Micro 27(3): 8-29 (2007)
[j55]
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Energy saving through a simple load control mechanism. SIGARCH Comput. Archit. News 35(4): 29-36 (2007)
[j54]
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Oliverio J. Santana, Alex Ramírez, Mateo Valero:
Enlarging Instruction Streams. IEEE Trans. Computers 56(10): 1342-1357 (2007)
[c148]
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Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero:
A Flexible Heterogeneous Multi-Core Architecture. PACT 2007: 13-24
[c147]
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Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero:
FAME: FAirly MEasuring Multithreaded Architectures. PACT 2007: 305-316
[c146]
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Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418
[c145]
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Runahead Threads: Reducing Resource Contention in SMT Processors. PACT 2007: 423
[c144]
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Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero:
Implicit Transactional Memory in Kilo-Instruction Multiprocessors. Asia-Pacific Computer Systems Architecture Conference 2007: 339-353
[c143]
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Sasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Hardware Transactional Memory with Operating System Support, HTMOS. Euro-Par Workshops 2007: 8-17
[c142]
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Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero:
HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications. IISWC 2007: 120-125
[c141]
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Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero:
Microarchitectural Support for Speculative Register Renaming. IPDPS 2007: 1-10
[c140]
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Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero:
Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications. ISPASS 2007: 62-71
[c139]
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Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Transactional Memory and OpenMP. IWOMP 2007: 37-53
[c138]
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Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero:
Multithreaded software transactional memory and OpenMP. MEDEA@PACT 2007: 81-88
[c137]
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Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero:
On the Problem of Minimizing Workload Execution Time in SMT Processors. ICSAMOS 2007: 66-73
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Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177
[c135]
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Nehir Sönmez, Cristian Perfumo, Srdjan Stipic, Adrián Cristal, Osman S. Unsal, Mateo Valero:
unreadTVar: Extending Haskell Software Transactional Memory for Performance. Trends in Functional Programming 2007: 89-104
2006
[j53]
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Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé:
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. IEEE Comput. Archit. Lett. 5(1): 14-17 (2006)
[j52]
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Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications. J. Embed. Comput. 2(1): 77-82 (2006)
[j51]
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Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero:
A DRAM/SRAM Memory Scheme for Fast Packet Buffers. IEEE Trans. Computers 55(5): 588-602 (2006)
[j50]
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Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Trans. Computers 55(7): 785-799 (2006)
[c134]
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Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero:
Branch predictor guided instruction decoding. PACT 2006: 202-211
[c133]
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Kilo-instruction processors, runahead and prefetching. Conf. Computing Frontiers 2006: 269-278
[c132]
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Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero:
Speculative early register release. Conf. Computing Frontiers 2006: 291-302
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Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero:
A decoupled KILO-instruction processor. HPCA 2006: 53-64
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Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero:
Performance Analysis of Sequence Alignment Applications. IISWC 2006: 51-60
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Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
A simple speculative load control mechanism for energy saving. MEDEA@PACT 2006: 29-36
2005
[j49]
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Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero:
Hardware support for early register release. Int. J. High Perform. Comput. Netw. 3(2/3): 83-94 (2005)
[j48]
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Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero:
Better Branch Prediction Through Prophet/Critic Hybrids. IEEE Micro 25(1): 80-89 (2005)
[j47]
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Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero:
Kilo-Instruction Processors: Overcoming the Memory Wall. IEEE Micro 25(3): 48-57 (2005)
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Alex Pajuelo, Antonio González, Mateo Valero:
Speculative execution for hiding memory latency. SIGARCH Comput. Archit. News 33(3): 49-56 (2005)
[j45]
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Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications. SIGARCH Comput. Archit. News 33(3): 57-62 (2005)
[j44]
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Esther Salamí, Mateo Valero:
Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications. ACM Trans. Archit. Code Optim. 2(2): 199-219 (2005)
[j43]
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Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
Software Trace Cache. IEEE Trans. Computers 54(1): 22-35 (2005)
[j42]
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Carlos Álvarez, Jesús Corbal, Mateo Valero:
Fuzzy Memoization for Floating-Point Multimedia Applications. IEEE Trans. Computers 54(7): 922-927 (2005)
[c128]
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Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero:
Architectural impact of stateful networking applications. ANCS 2005: 11-18
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Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Architectural support for real-time task scheduling in SMT processors. CASES 2005: 166-176
[c126]
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Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luís Villa:
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. ICCD 2005: 647-653
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Esther Salamí, Mateo Valero:
A Vector-µSIMD-VLIW Architecture for Multimedia Applications. ICPP 2005: 69-77
[c124]
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Carmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero:
A Complexity-Effective Simultaneous Multithreading Architecture. ICPP 2005: 157-164
[c123]
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Enrique Vallejo, Marco Galluzzi, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero:
Implementing Kilo-Instruction Multiprocessors. ICPS 2005: 325-336
[c122]
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Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum:
An asymmetric clustered processor based on value content. ICS 2005: 61-70
[c121]
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Ayose Falcón, Alex Ramírez, Mateo Valero:
Effective Instruction Prefetching via Fetch Prestaging. IPDPS 2005
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Alex Pajuelo, Antonio González, Mateo Valero:
Control-Flow Independence Reuse via Dynamic Vectorization. IPDPS 2005
[c119]
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Oliverio J. Santana, Alex Ramírez, Mateo Valero:
Multiple Stream Prediction. ISHPC 2005: 1-16
[c118]
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Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero:
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. ISHPC 2005: 56-67
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Miquel Pericàs, Adrián Cristal, Rubén González, Alexander V. Veidenbaum, Mateo Valero:
Decoupled State-Execute Architecture. ISHPC 2005: 68-78
[c116]
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Javier Verdú, Mario Nemirovsky, Jorge García-Vidal, Mateo Valero:
Workload Characterization of Stateful Networking Applications. ISHPC 2005: 130-141
[c115]
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Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero:
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. ISPASS 2005: 167-176
[c114]
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Raimir Holanda, Javier Verdú, Jorge García-Vidal, Mateo Valero:
Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering. ISPASS 2005: 219-225
[e8]
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Nader Bagherzadeh, Mateo Valero, Alex Ramírez:
Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005. ACM 2005, ISBN 1-59593-019-1 [contents]
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Thomas M. Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer:
High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings. Lecture Notes in Computer Science 3793, Springer 2005, ISBN 3-540-30317-0 [contents]
2004
[j41]
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Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luís Villa:
A partitioned instruction queue to reduce instruction wakeup energy. Int. J. High Perform. Comput. Netw. 1(4): 153-161 (2004)
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Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
High-performance and low-power VLIW cores for numerical computations. Int. J. High Perform. Comput. Netw. 1(4): 171-179 (2004)
[j39]
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Adrián Cristal, Josep Llosa, Mateo Valero, Daniel Ortega:
Future ILP processors. Int. J. High Perform. Comput. Netw. 2(1): 1-10 (2004)
[j38]
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Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero:
A latency-conscious SMT branch prediction architecture. Int. J. High Perform. Comput. Netw. 2(1): 11-21 (2004)
[j37]
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Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
Optimising long-latency-load-aware fetch policies for SMT processors. Int. J. High Perform. Comput. Netw. 2(1): 45-54 (2004)
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Daniel Ortega, Mateo Valero, Eduard Ayguadé:
Dynamic Memory Instruction Bypassing. Int. J. Parallel Program. 32(3): 199-224 (2004)
[j35]
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Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. Int. J. Parallel Program. 32(6): 447-474 (2004)
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Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández:
QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24(4): 24-31 (2004)
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Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero:
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. SIGARCH Comput. Archit. News 32(3): 3-10 (2004)
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Oliverio J. Santana, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
A low-complexity fetch architecture for high-performance superscalar processors. ACM Trans. Archit. Code Optim. 1(2): 220-245 (2004)
[j31]
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Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez:
Toward kilo-instruction processors. ACM Trans. Archit. Code Optim. 1(4): 389-417 (2004)
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Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero:
Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004)
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Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Register Constrained Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 15(5): 417-430 (2004)
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Oliverio J. Santana, Alex Ramírez, Mateo Valero:
Reducing Fetch Architecture Complexity Using Procedure Inlining. Interaction between Compilers and Computer Architectures 2004: 97-106
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Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero:
A first glance at Kilo-instruction based multiprocessors. Conf. Computing Frontiers 2004: 212-221
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Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Predictable performance in SMT processors. Conf. Computing Frontiers 2004: 433-443
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Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51
[c109]
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Adrián Cristal, Oliverio J. Santana, Mateo Valero:
Maintaining Thousands of In-flight Instructions. Euro-Par 2004: 9-20
[c108]
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Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Feasibility of QoS for SMT. Euro-Par 2004: 535-540
[c107]
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Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
Enabling SMT for real-time embedded systems. EUSIPCO 2004: 1341-1344
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Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero:
Out-of-Order Commit Processors. HPCA 2004: 48-59
[c105]
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Ayose Falcón, Alex Ramírez, Mateo Valero:
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. HPCA 2004: 244-253
[c104]
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Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. IPDPS 2004
[c103]
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Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero:
Prophet/Critic Hybrid Branch Prediction. ISCA 2004: 250-263
[c102]
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Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero:
A Content Aware Integer Register File Organization. ISCA 2004: 314-324
[c101]
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Alex Pajuelo, Antonio González, Mateo Valero:
Speculative execution for hiding memory latency. MEDEA@PACT 2004: 49-56
[c100]
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Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications. MEDEA@PACT 2004: 57-62
[c99]
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Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
Dynamically Controlled Resource Allocation in SMT Processors. MICRO 2004: 171-182
[c98]
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Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero:
An Optimized Front-End Physical Register File with Banking and Writeback Filtering. PACS 2004: 1-14
[c97]
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Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. SAMOS 2004: 88-97
[c96]
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Esther Salamí, Mateo Valero:
Initial Evaluation of Multimedia Extensions on VLIW Architectures. SAMOS 2004: 403-412
[c95]
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Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero:
Evaluating kilo-instruction multiprocessors. WMPI 2004: 72-79
2003
[j28]
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Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero:
A Case for Resource-conscious Out-of-order Processors. IEEE Comput. Archit. Lett. 2 (2003)
[j27]
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Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero:
A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. Theory Comput. Syst. 36(5): 575-593 (2003)
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Jorge Garcia, Llorenç Cerdà, Jesús Corbal, Mateo Valero:
A conflict-free memory banking architecture for fast VOQ packet buffers. GLOBECOM 2003: 4158-4162
[c93]
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Daniel Ortega, Eduard Ayguadé, Mateo Valero:
Dynamic memory instruction bypassing. ICS 2003: 316-325
[c92]
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Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Hierarchical Clustered Register File Organization for VLIW Processors. IPDPS 2003: 77
[c91]
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Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero:
Kilo-instruction Processors. ISHPC 2003: 10-25
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Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero:
Improving Memory Latency Aware Fetch Policies for SMT Processors. ISHPC 2003: 70-85
[c89]
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Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero:
Tolerating Branch Predictor Latency on SMT. ISHPC 2003: 86-98
[c88]
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Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luís Villa, Mateo Valero:
A Simple Low-Energy Instruction Wakeup Mechanism. ISHPC 2003: 99-112
[c87]
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Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ISHPC 2003: 113-126
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Sally A. McKee, Zhen Fang, Mateo Valero:
An MPEG-4 performance study for non-SIMD, general purpose architectures. ISPASS 2003: 49-57
[c85]
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Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero:
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. MICRO 2003: 373-386
2002
[j26]
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Carlos Álvarez, Jesús Corbal, Esther Salamí, Mateo Valero:
Initial Results on Fuzzy Floating Point Computation for Multimedia Processors. IEEE Comput. Archit. Lett. 1 (2002)
[j25]
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Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas:
Software Trace Cache for Commercial Applications. Int. J. Parallel Program. 30(5): 373-395 (2002)
[j24]
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Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero:
Errata on "Measuring Experimental Error in Microprocessor Simulation". SIGARCH Comput. Archit. News 30(1): 2-4 (2002)
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Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero:
Cost-Effective Compiler Directed Memory Prefetching and Bypassing. IEEE PACT 2002: 189-198
[c83]
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Esther Salamí, Jesús Corbal, Carlos Álvarez, Mateo Valero:
Cost effective memory disambiguation for multimedia codes. CASES 2002: 117-126
[c82]
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Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero:
A Comparative Study of Redundancy in Trace Caches (Research Note). Euro-Par 2002: 512-516
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Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero:
Hardware Schemes for Early Register Release. ICPP 2002: 5-13
[c80]
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Alex Pajuelo, Antonio González, Mateo Valero:
Speculative Dynamic Vectorization. ISCA 2002: 271-280
[c79]
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Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero:
A Comprehensive Analysis of Indirect Branch Prediction. ISHPC 2002: 133-145
[c78]
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Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero:
Studying New Ways for Improving Adaptive History Length Branch Predictors. ISHPC 2002: 271-280
[c77]
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Jesús Corbal, Roger Espasa, Mateo Valero:
Three-dimensional memory vectorization for high bandwidth media memory systems. MICRO 2002: 149-160
[c76]
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Alex Ramírez, Oliverio J. Santana, Josep Lluís Larriba-Pey, Mateo Valero:
Fetching instruction streams. MICRO 2002: 371-382
2001
[j23]
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Sriram Vajapeyam, Mateo Valero:
Early 21st Century Processors - Guest Editors' Introduction. Computer 34(4): 47-50 (2001)
[j22]
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Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
Instruction fetch architectures and code layout optimizations. Proc. IEEE 89(11): 1588-1609 (2001)
[j21]
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Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero:
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News 29(5): 9-12 (2001)
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Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt:
Lifetime-Sensitive Modulo Scheduling in a Production Environment. IEEE Trans. Computers 50(3): 234-249 (2001)
[j19]
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David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. IEEE Trans. Computers 50(10): 1033-1051 (2001)
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Jesús Corbal, Roger Espasa, Mateo Valero:
On the Efficiency of Reductions in µ-SIMD Media Extensions. IEEE PACT 2001: 83-94
[c74]
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Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
Branch Prediction Using Profile Data. Euro-Par 2001: 386-393
[c73]
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Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana:
Topic 15+20: Multimedia and Embedded Systems. Euro-Par 2001: 651-652
[c72]
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Jesús Corbal, Roger Espasa, Mateo Valero:
DLP + TLP Processors for the Next Generation of Media Workloads. HPCA 2001: 219-228
[c71]
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Carlos Álvarez, Jesús Corbal, Esther Salamí, Mateo Valero:
On the potential of tolerant region reuse for multimedia applications. ICS 2001: 218-228
[c70]
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Daniel Ortega, Mateo Valero, Eduard Ayguadé:
A novel renaming mechanism that boosts software prefetching. ICS 2001: 501-510
[c69]
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Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep Lluís Larriba-Pey, P. Geoffrey Lowney, Mateo Valero:
Code layout optimizations for transaction processing workloads. ISCA 2001: 155-164
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Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
MIRS: Modulo Scheduling with Integrated Register Spilling. LCPC 2001: 239-253
[c67]
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Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Modulo scheduling with integrated register spilling for clustered VLIW architectures. MICRO 2001: 160-169
[c66]
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Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero:
A cost effective architecture for vectorizable numerical and multimedia applications. SPAA 2001: 103-112
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Lionel M. Ni, Mateo Valero:
Proceedings of the 2001 International Conference on Parallel Processing, ICPP 2002, 3-7 September 2001, Valencia, Spain. IEEE Computer Society 2001, ISBN 0-7695-1257-7 [contents]
2000
[j18]
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Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism 2 (2000)
[c65]
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Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
The Effect of Code Reordering on Branch Prediction. IEEE PACT 2000: 189-198
[c64]
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Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis:
Parallel Computer Architecture. Euro-Par 2000: 537-538
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Carlos Navarro, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
On the Performance of Fetch Engines Running DSS Workloads. Euro-Par 2000: 940-949
[c62]
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Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
Trace Cache Redundancy: Red & Blue Traces. HPCA 2000: 325-333
[c61]
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José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham:
Multiple-banked register file architectures. ISCA 2000: 316-325
[c60]
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Mateo Valero:
Architectures for One Billion of Transistors. ISSS 2000: 62
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Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Two-level hierarchical register file organization for VLIW processors. MICRO 2000: 137-146
[c58]
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Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Improved spill code generation for software pipelined loops. PLDI 2000: 134-144
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Mateo Valero, Viktor K. Prasanna, Sriram Vajapeyam:
High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings. Lecture Notes in Computer Science 1970, Springer 2000, ISBN 3-540-41429-0 [contents]
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Mateo Valero, Kazuki Joe, Masaru Kitsuregawa, Hidehiko Tanaka:
High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings. Lecture Notes in Computer Science 1940, Springer 2000, ISBN 3-540-41128-3 [contents]

1990 – 1999

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What is the meaning of the colors in the publication lists?

1999
[j17]
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Veljko M. Milutinovic, Mateo Valero:
Enhancing and Exploiting the Locality. IEEE Trans. Computers 48(2): 97-99 (1999)
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Roger Espasa, Mateo Valero:
A Simulation Study of Decoupled Vector Architectures. J. Supercomput. 14(2): 124-152 (1999)
[c57]
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Daniel Ortega, Ivan Martel, Venkata Krishnan, Eduard Ayguadé, Mateo Valero:
Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures. IEEE PACT 1999: 117-124
[c56]
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Pascal Sainrat, Mateo Valero:
Instruction-Level Parallelism and Uniprocessor Architecture - Introduction. Euro-Par 1999: 1241-1242
[c55]
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David López, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. ICPP 1999: 22-29
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Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas:
Optimization of Instruction Fetch for Decision Support Workloads. ICPP 1999: 238-245
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Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero:
Adding a vector unit to a superscalar processor. International Conference on Supercomputing 1999: 1-10
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Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero:
Software trace cache. International Conference on Supercomputing 1999: 119-126
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Ivan Martel, Daniel Ortega, Eduard Ayguadé, Mateo Valero:
Increasing effective IPC by exploiting distant parallelism. International Conference on Supercomputing 1999: 348-355
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Jesús Corbal, Roger Espasa, Mateo Valero:
Exploiting a New Level of DLP in Multimedia Applications. MICRO 1999: 72-79
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Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186-192
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Jesús Corbal, Roger Espasa, Mateo Valero:
MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. SC 1999: 15
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Theodore S. Papatheodorou, Mateo Valero, Constantine D. Polychronopoulos, Yoichi Muraoka, Jesús Labarta:
Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999. ACM 1999, ISBN 1-58113-164-X [contents]
1998
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Josep Llosa, Eduard Ayguadé, Mateo Valero:
Quantitative Evaluation of Register Pressure on Software Pipelined Loops. Int. J. Parallel Program. 26(2): 121-142 (1998)
[j14]
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Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Modulo Scheduling with Reduced Register Pressure. IEEE Trans. Computers 47(6): 625-638 (1998)
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Jesús Corbal, Roger Espasa, Mateo Valero:
Command Vector Memory Systems: High Performance at Low Cost. IEEE PACT 1998: 68-
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Antonio González, José González, Mateo Valero:
Virtual-Physical Registers. HPCA 1998: 175-184
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Luís Villa, Roger Espasa, Mateo Valero:
A Performance Study of Out-of-order Vector Architectures and Short Registers. International Conference on Supercomputing 1998: 37-44
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Roger Espasa, Mateo Valero, James E. Smith:
Vector Architectures: Past, Present and Future. International Conference on Supercomputing 1998: 425-432
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David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Resource Widening Versus Replication: Limits and Performance-cost Trade-off. International Conference on Supercomputing 1998: 441-448
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David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. MICRO 1998: 237-246
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Francisca Quintana, Roger Espasa, Mateo Valero:
A case for merging the ILP and DLP paradigms. PDP 1998: 217-224
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Luís Villa, Roger Espasa, Mateo Valero:
Effective usage of vector registers in decoupled vector architectures. PDP 1998: 495-501
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Luís Villa, Roger Espasa, Mateo Valero:
Registers Size Influence on Vector Architectures. VECPAR 1998: 439-451
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Francisca Quintana, Roger Espasa, Mateo Valero:
An ISA Comparison Between Superscalar and Vector Processors. VECPAR 1998: 548-560
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Mateo Valero, Gurindar S. Sohi, Doug DeGroot:
Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998. IEEE Computer Society 1998, ISBN 0-8186-8491-7 [contents]
1997
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Roger Espasa, Mateo Valero:
Exploiting instruction- and data-level parallelism. IEEE Micro 17(5): 20-27 (1997)
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Luís Villa, Roger Espasa, Mateo Valero:
Effective Usage of Vector Registers in Advanced Vector Architectures. IEEE PACT 1997: 250-260
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F. Jesús Sánchez, Antonio González, Mateo Valero:
Static Locality Analysis for Cache Management. IEEE PACT 1997: 261-271
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Roger Espasa, Mateo Valero:
Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. HiPC 1997: 350-357
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Antonio González, Mateo Valero, José González, Teresa Monreal Arnal:
Virtual registers. HiPC 1997: 364-369
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Roger Espasa, Mateo Valero:
Multithreaded Vector Architectures. HPCA 1997: 237-248
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David López, Mateo Valero, Josep Llosa, Eduard Ayguadé:
Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. International Conference on Supercomputing 1997: 12-19
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Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa:
Eliminating Cache Conflict Misses through XOR-Based Placement Functions. International Conference on Supercomputing 1997: 76-83
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Roger Espasa, Mateo Valero:
A Victim Cache for Vector Registers. International Conference on Supercomputing 1997: 293-300
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Roger Espasa, Mateo Valero, James E. Smith:
Out-of-Order Vector Architectures. MICRO 1997: 160-170
1996
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Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero:
Swing module scheduling: a lifetime-sensitive approach. IEEE PACT 1996: 80-86
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Roger Espasa, Mateo Valero:
Decoupled Vector Architectures. HPCA 1996: 281-290
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Josep Llosa, Mateo Valero, Eduard Ayguadé:
Heuristics for Register-Constrained Software Pipelining. MICRO 1996: 250-261
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Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Loop Parallelization: Revisiting Framework of Unimodular Transformations. PDP 1996: 420-428
1995
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Eduard Ayguadé, Jesús Labarta, Jordi Garcia, Mercè Gironés, Mateo Valero:
Analyzing reference patterns in automatic data distribution tools. Int. J. Parallel Program. 23(6): 515-535 (1995)
[j11]
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Mateo Valero, Tomás Lang, Montse Peiron, Eduard Ayguadé:
Conflict-Free Access for Streams in Multimodule Memories. IEEE Trans. Computers 44(5): 634-646 (1995)
[c24]
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Cristina Barrado, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Automatic generation of loop scheduling for VLIW. PACT 1995: 306-309
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Josep Llosa, Mateo Valero, Eduard Ayguadé:
Non-Consistent Dual Register Files to Reduce Register Pressure. HPCA 1995: 22-31
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Antonio González, Carlos Aliagas, Mateo Valero:
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. International Conference on Supercomputing 1995: 338-347
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Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang:
Vector Multiprocessors with Arbitrated Memory Access. ISCA 1995: 243-252
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Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Hypernode reduction modulo scheduling. MICRO 1995: 350-360
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Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé:
Quantitative analysis of vector code. PDP 1995: 452-463
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Mateo Valero:
Proceedings of the 9th international conference on Supercomputing, ICS 1995, Barcelona, Spain, July 3-7, 1995. ACM 1995, ISBN 0-89791-728-6 [contents]
1994
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Mateo Valero, Eduard Ayguadé, Montse Peiron:
Network Synchronization and Out-of-Order Access to Vectors. Parallel Process. Lett. 4: 405-415 (1994)
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Mateo Valero, Montse Peiron, Eduard Ayguadé:
Memory Access Synchronization in Vector Multiprocessors. CONPAR 1994: 414-425
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Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé:
Using Sacks to Organize Registers in VLIW Machines. CONPAR 1994: 628-639
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Montse Peiron, Mateo Valero, Eduard Ayguadé:
Synchronized access to streams in SIMD vector multiprocessors. International Conference on Supercomputing 1994: 23-32
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Eduard Ayguadé, Jordi Garcia, Mercè Gironés, Jesús Labarta, Jordi Torres, Mateo Valero:
Detecting and Using Affinity in an Automatic Data Distribution Tool. LCPC 1994: 61-75
[c14]
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Mateo Valero, Montse Peiron, Eduard Ayguadé:
Access To Vectors In Multi-module Memories. PDP 1994: 228-236
1993
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Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang:
Conflict-free access to streams in multiprocessor systems. Microprocess. Microprogramming 38(1-5): 119-130 (1993)
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Mateo Valero, Jordi Cortadella, Antonio González:
Chairmen's introduction. Microprocess. Microprogramming 38(1-5) (1993)
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Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Align and Distribute-based Linear Loop Transformations. LCPC 1993: 321-339
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Mateo Valero, Montse Peiron, Eduard Ayguadé:
Access to streams in multiprocessor systems. PDP 1993: 310-316
1992
[j7]
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Miguel Valero-García, Juan J. Navarro, José María Llabería, Mateo Valero, Tomás Lang:
A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. J. VLSI Signal Process. 4(1): 7-25 (1992)
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Mateo Valero, Tomás Lang, Eduard Ayguadé:
Conflict-free access of vectors with power-of-two strides. ICS 1992: 149-156
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Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro:
Increasing the Number of Strides for Conflict-Free Vector Access. ISCA 1992: 372-381
1991
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Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé:
Conflict-Free Strides for Vectors in Matched Memories. Parallel Process. Lett. 1: 95-102 (1991)
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Miguel Valero-García, Juan J. Navarro, José J. M. Liabería, Mateo Valero, Tomás Lang:
Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units. Algorithms and Parallel VLSI Architectures 1991: 25-38
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Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero:
On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. EDMCC 1991: 173-182
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Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería:
Balanced Loop Partitioning Using GTS. LCPC 1991: 298-312
1990
[c6]
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Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero:
Implementation of systolic algorithms using pipelined functional units. ASAP 1990: 272-283

1980 – 1989

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1989
[j5]
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Fernando J. Nuñez, Mateo Valero:
A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem. J. VLSI Signal Process. 1(2): 153-162 (1989)
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Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero:
Systematic Hardware Adaptation of Systolic Algorithms. ISCA 1989: 96-104
1987
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Juan J. Navarro, José M. Llabería, Mateo Valero:
Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors. Computer 20(7): 77-89 (1987)
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Miguel Angel Fiol, J. Luis A. Yebra, Ignacio Alegre, Mateo Valero:
A Discrete Optimization Problem in Local Networks and Data Alignment. IEEE Trans. Computers 36(6): 702-713 (1987)
1986
[c4]
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Juan J. Navarro, José M. Llabería, Mateo Valero:
Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. ICPP 1986: 676-683
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Juan J. Navarro, José M. Llabería, Mateo Valero:
Computing Size-Independent Matrix Problems on Systolic Array Processors. ISCA 1986: 271-278
1985
[c2]
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José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta:
Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. ISCA 1985: 414-421
1983
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Tomás Lang, Mateo Valero, Miguel Angel Fiol:
Reduction of Connections for Multibus Organization. IEEE Trans. Computers 32(8): 707-716 (1983)
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Mateo Valero, José María Llabería, Jesús Labarta, Emilio Sanvicente, Tomás Lang:
A performance evaluation of the multiple bus network for multiprocessor systems. SIGMETRICS 1983: 200-206
1982
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Tomás Lang, Mateo Valero, Ignacio Alegre:
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors. IEEE Trans. Computers 31(12): 1227-1234 (1982)

Coauthor Index

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