default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID6. Conference On Computing Frontiers 2010: Bertinoro, Italy
- Nancy M. Amato, Hubertus Franke, Paul H. J. Kelly:
Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010. ACM 2010, ISBN 978-1-4503-0044-5
Neuroscience
- Yong Cao, Debprakash Patnaik, Sean P. Ponce, Jeremy S. Archuleta, Patrick Butler, Wu-chun Feng, Naren Ramakrishnan
:
Towards chip-on-chip neuroscience: fast mining of neuronal spike streams using graphics hardware. 1-10 - Javier Navaridas, Luis A. Plana, José Miguel-Alonso, Mikel Luján, Stephen B. Furber:
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network. 11-20 - Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Stephen B. Furber:
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. 21-30
Operating systems and storage
- Juan Carlos Saez, Alexandra Fedorova, Manuel Prieto, Hugo Vegas:
Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors. 31-40 - Miaoqing Huang, Olivier Serres, Vikram K. Narayana, Tarek A. El-Ghazawi, Gregory B. Newby:
Efficient cache design for solid-state drives. 41-50
Keynote
- Daniela Rus:
Programmable matter with self-reconfiguring robots. 51-52
Concurrency and scheduling
- Daniel Cederman, Philippas Tsigas:
Supporting lock-free composition of concurrent data objects. 53-62 - Yinglong Xia, Viktor K. Prasanna:
Collaborative scheduling of DAG structured computations on multicore processors. 63-72
Poster session
- José L. Abellán, Juan Fernández, Manuel E. Acacio:
Efficient and scalable barrier synchronization for many-core CMPs. 73-74 - Andrew D. Brown, Steve B. Furber, Jeff S. Reeve, Peter R. Wilson, Mark Zwolinski, John E. Chad, Luis A. Plana, David R. Lester:
A communication infrastructure for a million processor machine. 75-76 - Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su:
A hyperscalar multi-core architecture. 77-78 - Xiufeng Sui, Junmin Wu, Guoliang Chen, Yixuan Tang, Xiaodong Zhu:
Augmenting cache partitioning with thread-aware insertion/promotion policies to manage shared caches. 79-80 - Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose:
Performance and power evaluation of an in-line accelerator. 81-82 - Ananth Nallamuthu, Melissa C. Smith, Scott S. Hampton, Pratul K. Agarwal, Sadaf R. Alam:
Energy efficient biomolecular simulations with FPGA-based reconfigurable computing. 83-84 - Jayanth Gummaraju, Ben Sander, Laurent Morichetti, Benedict R. Gaster, Lee W. Howes:
Efficient implementation of GPGPU synchronization primitives on CPUs. 85-86 - Antonino Tumeo, Oreste Villa, Donatella Sciuto:
Efficient pattern matching on GPUs for intrusion detection systems. 87-88 - Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve B. Furber:
Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker. 89-90 - Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer:
Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture. 91-92 - Martin Omaña, Daniele Rossi, Nicolò Bosio, Cecilia Metra:
Novel low-cost aging sensor. 93-94 - Flavius Opritoiu, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu:
A high-speed AES architecture implementation. 95-96 - Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart D. Theelen, Bart Mesman, Henk Corporaal:
A predictable communication assist. 97-98 - Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos:
Exploitation of nested thread-level speculative parallelism on multi-core systems. 99-100 - Pandya Lakshman:
Combining deblurring and denoising for handheld HDR imaging in low light conditions. 101-102 - Vincenzo D. Cunsolo, Salvatore Distefano, Antonio Puliafito, Marco Scarpa:
From volunteer to cloud computing: cloud@home. 103-104 - Antonio Celesti, Massimo Villari, Antonio Puliafito:
Design of a cloud naming framework. 105-106 - Andrea Bosin, Nicoletta Dessì, Madusudhanan Bairappan:
A service-based approach for the execution of scientific workflows in grids. 107-108 - Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini:
Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints. 109-110 - Yufeng Nie, Lei Wang, Weiwei Zhang:
A portable parallel finite element simulation system. 111-112 - Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche:
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. 113-114 - Simone Pellegrini, Thomas Fahringer, Herbert Jordan, Hans Moritsch:
Automatic tuning of MPI runtime parameter settings by using machine learning. 115-116 - David A. Penry, Daniel J. Richins, Tyler S. Harris, David Greenland, Koy D. Rehme:
Exposing parallelism and locality in a runtime parallel optimization framework. 117-118 - Cupertino Miranda, Philippe Dumont, Albert Cohen, Marc Duranton, Antoniu Pop:
ERBIUM: a deterministic, concurrent intermediate representation for portable and scalable performance. 119-120
Caches and branches 1
- Li Zhao, Ravi R. Iyer, Srihari Makineni, Don Newell, Liqun Cheng:
NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies. 121-130 - Mohamed Zahran, Sally A. McKee:
Global management of cache hierarchies. 131-140 - Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras:
Where replacement algorithms fail: a thorough analysis. 141-150
Keynote
- Özalp Babaoglu:
Nature-inspired techniques for self-organization in dynamic networks. 151-152
Caches and branches 2
- Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero:
Load balancing using dynamic cache allocation. 153-164 - Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg:
EXACT: explicit dynamic-branch prediction with active updates. 165-176
Parallel systems
- James Dinan, Pavan Balaji, Ewing L. Lusk, P. Sadayappan, Rajeev Thakur:
Hybrid parallel programming with MPI and unified parallel C. 177-186 - Richard W. Neill, Alexander Shabarshin, Luca P. Carloni:
A heterogeneous parallel system running open mpi on a broadband network of embedded set-top devices. 187-196 - Oliver Trachsel, Thomas R. Gross:
Variant-based competitive parallel execution of sequential programs. 197-206 - Vinod Tipparaju, Edoardo Aprà, Weikuan Yu, Jeffrey S. Vetter:
Enabling a highly-scalable global address space model for petascale computing. 207-216
Processor architecture
- Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos:
On-chip communication and synchronization mechanisms with cache-integrated network interfaces. 217-226 - Patrick Anthony La Fratta, Peter M. Kogge:
Models for generating locality-tuned traveling threads for a hierarchical multi-level heterogeneous multicore. 227-236 - Pierre Michaud, Yiannakis Sazeides, André Seznec:
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. 237-246
Quantum computing
- Alina Vasilieva, Taisia Mischenko-Slatenkova:
High precision quantum query algorithm for computing AND-based boolean functions. 247-256 - Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens:
Reversible online BIST using bidirectional BILBO. 257-266
Power 1
- Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs. 267-276 - Michael Moeng, Rami G. Melhem:
Applying statistical machine learning to multicore voltage & frequency scaling. 277-286
Power 2
- Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras:
Interval-based models for run-time DVFS orchestration in superscalar processors. 287-296 - Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt:
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. 297-308 - In Hwan Doh, Young Jin Kim, Jung Soo Park, Eunsam Kim, Jongmoo Choi, Donghee Lee, Sam H. Noh:
Towards greener data centers with storage class memory: minimizing idle power waste through coarse-grain management in fine-grain scale. 309-318
Fault tolerance and parallel applications
- Demid Borodin, Ben H. H. Juurlink:
Protective redundancy overhead reduction using instruction vulnerability factor. 319-326 - Danilo Pani, Simone Secchi, Luigi Raffo:
Self organization on a swarm computing fabric: a new way to look at fault tolerance. 327-336 - Herbert Jordan, Radu Prodan, Vlad Nae, Thomas Fahringer:
Dynamic load management for MMOGs in distributed environments. 337-346 - Andrew Ian Stone, Steve DiBenedetto, Michelle Mills Strout, Daniel Massey:
Scalable simulation of complex network routing policies. 347-356
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-07 01:31 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
