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ORCIDSIGARCH Computer Architecture News, Volume 35
Volume 35, Number 1, March 2007
- Dean M. Tullsen, Rakesh Kumar, Norman P. Jouppi:
Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06). 2 - Aqeel Mahesri, Nicholas J. Wang, Sanjay J. Patel:
Hardware support for software controlled multithreading. 3-12 - Xudong Shi, Feiqi Su, Jih-Kwon Peir, Ye Xia, Zhen Yang:
CMP cache performance projection: accessibility vs. capacity. 13-20 - Fei Guo, Hari Kannan, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Don Newell, Yan Solihin, Christos Kozyrakis:
From chaos to QoS: case studies in CMP resource management. 21-30 - Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura:
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. 31-38 - M. M. Waliullah, Per Stenström:
Starvation-free commit arbitration policies for transactional memory systems. 39-46 - Cesare Ferri, Tali Moreshet, R. Iris Bahar
, Luca Benini, Maurice Herlihy:
A hardware/software framework for supporting transactional memory in a MPSoC environment. 47-54 - Sean Rul, Hans Vandierendonck, Koen De Bosschere:
Function level parallelism driven by data dependencies. 55-62
- John L. Henning:
Guest editor's introduction. 63-64 - John L. Henning:
SPEC CPU suite growth: an historical perspective. 65-68 - Aashish Phansalkar, Ajay Joshi, Lizy K. John:
Subsetting the SPEC CPU2006 benchmark suite. 69-76 - Michael Wong:
C++ benchmarks in SPEC CPU2006. 77-83 - John L. Henning:
SPEC CPU2006 memory footprint. 84-89 - Darryl Gove:
CPU2006 working set size. 90-96 - Wendy Korn, Moon S. Chang:
SPEC CPU2006 sensitivity to memory page sizes. 97-101 - Reinhold Weicker, John L. Henning:
Subroutine profiling results for the CPU2006 benchmarks. 102-111 - Dong Ye, Joydeep Ray, David R. Kaeli:
Characterization of file I/O activity for SPEC CPU2006. 112-117 - John L. Henning:
Performance counters and development of SPEC CPU2006. 118-121 - Darryl Gove, Lawrence Spracklen:
Evaluating the correspondence between training and reference workloads in SPEC CPU2006. 122-129 - Cloyce D. Spradling:
SPEC CPU2006 benchmark tools. 130-134 - Swaroop Sridhar, Jonathan S. Shapiro, Prashanth P. Bungale:
HDTrans: a low-overhead dynamic translator. 135-140 - Jun Yan, Wei Zhang:
Hybrid multi-core architecture for boosting single-threaded performance. 141-148
- Mark Thorson:
Internet nuggets. 149-154
Volume 35, Number 2, May 2007
- Dean M. Tullsen, Brad Calder:
34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA. ACM 2007, ISBN 978-1-59593-706-3 [contents]
Volume 35, Number 3, June 2007
- Aneesh Aggarwal, Pradip Bose, Mohamed Zahran:
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop. 1 - Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier:
Mapping streaming architectures on reconfigurable platforms. 2-8 - Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan:
Custom code generation for soft processors. 9-19 - Tameesh Suri:
Improving instruction level parallelism through reconfigurable units in superscalar processors. 20-27 - Hashem Hashemi Najaf-abadi, Eric Rotenberg:
Architectural contesting: exposing and exploiting temperamental behavior. 28-35 - Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai:
Deterministic high-speed root-hashing automaton matching coprocessor for embedded network processor. 36-43 - Fadi N. Sibai:
Performance analysis and workload characterization of the 3DMark05 benchmark on modern parallel computer platforms. 44-52
- Mark Thorson:
Internet nuggets. 53-55
Volume 35, Number 4, September 2007
- Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
MEmory performance: DEaling with applications, systems and architecture. 4-5 - K. Patrick Lorton, David S. Wise:
Analyzing block locality in Morton-order and Morton-hybrid matrices. 6-12 - Kaveh Jokar Deris, Amirali Baniasadi:
Investigating cache energy and latency break-even points in high performance processors. 13-20 - Jun Yan, Wei Zhang:
Evaluating instruction cache vulnerability to transient errors. 21-28 - Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Energy saving through a simple load control mechanism. 29-36 - Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Data prefetching in a cache hierarchy with high bandwidth and capacity. 37-44 - Haakon Dybdahl, Per Stenström, Lasse Natvig:
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. 45-52 - Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström:
Improving power efficiency of D-NUCA caches. 53-58
- Mark Thorson:
Internet nuggets. 59-62
Volume 35, Number 5, December 2007
- Kenji Kise, Toshinori Sato, Hironori Nakajo:
Introduction. 1-2 - Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita:
Optimal pipeline depth with pipeline stage unification adoption. 3-9 - Preetham Lakshmikanthan, Adrian Nunez:
VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies. 10-16 - Kiyofumi Tanaka, Takahiro Kawahara:
Leakage energy reduction in cache memory by data compression. 17-24 - Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai:
Preventing timing errors on register writes: mechanisms of detections and recoveries. 25-31 - Mihaela Malita, Gheorghe Stefan, Dominique Thiébaut:
Not multi-, but many-core: designing integral parallel architectures for embedded computation. 32-38 - Takefumi Miyoshi, Nobuhiko Sugino:
Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption. 39-44 - Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin:
VariaSim: simulating circuits and systems in the presence of process variability. 45-48 - Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan:
Future generation supercomputers I: a paradigm for node architecture. 49-60 - Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan:
Future generation supercomputers II: a paradigm for cluster architecture. 61-70
- Mark Thorson:
Internet nuggets. 71-73
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