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"Circuit design of a dual-versioning L1 data cache for optimistic concurrency."
Azam Seyedi et al. (2011)
- Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330
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