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ORCID6th HPCA 2000: Toulouse, France
- Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000. IEEE Computer Society 2000, ISBN 0-7695-0550-3
System Architecture Tradeoffs
- Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese:
Impact of Chip-Level Integration on Performance of OLTP Workloads. 3-14 - Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen:
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. 15-25 - Renato J. O. Figueiredo, José A. B. Fortes:
Impact of Heterogeneity on DSM Performance. 26-35
Memory and Cache
- Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis:
Design of a Parallel Vector Access Unit for SDRAM Memory Systems. 39-48 - Wayne A. Wong, Jean-Loup Baer:
Modified LRU Policies for Improving Second-Level Cache Behavior. 49-60 - Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez
, Adi Yoaz, Ronny Ronen:
eXtended Block Cache. 61-70
Networks
- Li-Shiuan Peh, William J. Dally:
Flit-Reservation Flow Control. 73-84 - Rafael Casado, Aurelio Bermúdez, Francisco J. Quiles, José L. Sánchez, José Duato:
Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks. 85-96 - Ki Hwan Yum, Aniruddha S. Vaidya, Chita R. Das, Anand Sivasubramaniam:
Investigating QoS Support for Traffic Mixes with the MediaWorm Router. 97-106
Multithreading and Microarchitecture
- James Burns, Jean-Luc Gaudiot:
Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight? 109-120 - Todd C. Mowry, Sherwyn R. Ramkissoon:
Software-Controlled Multithreading Using Informing Memory Operations. 121-132 - Ramon Canal, Joan-Manuel Parcerisa, Antonio González:
Dynamic Cluster Assignment Mechanisms. 133-142
Shared Memory
- Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph:
High-Throughput Coherence Controllers. 145-155 - Stefanos Kaxiras, Cliff Young:
Coherence Communication Prediction in Shared-Memory Multiprocessors. 156-167 - Ravi Rajwar, Alain Kägi, James R. Goodman:
Improving the Throughput of Synchronization by Insertion of Delays. 168-179
Software Techniques
- Marta Jiménez, José M. Llabería, Agustín Fernández:
On the Performance of Hand vs. Automatically Optimized Numerical Codes. 183-194 - Siddhartha Chatterjee, Sandeep Sen:
Cache-Efficient Matrix Transposition. 195-205 - Magnus Karlsson, Fredrik Dahlgren, Per Stenström:
A Prefetching Technique for Irregular Accesses to Linked Data Structures. 206-217 - Charles Lefurgy, Eva Piccininni, Trevor N. Mudge:
Reducing Code Size with Run-Time Decompression. 218-228
Prediction I
- Sang Jeong Lee, Yuan Wang, Pen-Chung Yew:
Decoupled Value Prediction on Trace Processors. 231-240 - Michael Haungs, Phil Sallee, Matthew K. Farrens:
Branch Transition Rate: A New Metric for Improved Branch Classification Analysis. 241-250 - Harish Patil, Joel S. Emer:
Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. 251-262
Parallel Systems
- Robert Stets, Sandhya Dwarkadas, Leonidas I. Kontothanassis, Umit Rencuzogullari, Michael L. Scott:
The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing. 265-276 - Peter M. Behr, S. Pletner, Angela C. Sodan:
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620. 277-286 - Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose:
A DSM Architecture for a Parallel Computer Cenju-4. 287-298
Prediction II
- Andreas Moshovos, Gurindar S. Sohi:
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. 301-312 - Henk Neefs, Hans Vandierendonck, Koenraad De Bosschere:
A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. 313-324 - Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
Trace Cache Redundancy: Red & Blue Traces. 325-333
Parallel Systems Performance
- Mustafa Uysal, Anurag Acharya, Joel H. Saltz:
Evaluation of Active Disks for Decision Support Databases. 337-348 - Franck Cappello, Olivier Richard, Daniel Etiemble:
Investigating the Performance of Two Programming Models for Clusters of SMP PCs. 349-359 - Robert P. Bosch Jr., Chris Stolte, Gordon Stoll, Mendel Rosenblum, Pat Hanrahan:
Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study. 360-371
Novel Architecture Issues
- Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens:
Register Organization for Media Processing. 375-386 - Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam:
Architectural Issues in Java Runtime Systems. 387-398 - Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam:
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches. 399-408 - Tzi-cker Chiueh, Prashant Pradhan:
Cache Memory Design for Network Processors. 409-418
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