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Benjamin P. Hershberg
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Journal Articles
- 2024
- [j16]Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro:
A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration. IEEE J. Solid State Circuits 59(3): 740-752 (2024) - 2022
- [j15]Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx:
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits 57(4): 1112-1124 (2022) - [j14]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57(7): 2068-2077 (2022) - 2021
- [j13]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits 56(4): 1227-1240 (2021) - [j12]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits 56(8): 2360-2374 (2021) - [j11]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2813-2826 (2021) - 2019
- [j10]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54(2): 403-416 (2019) - [j9]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54(3): 646-658 (2019) - 2018
- [j8]Ewout Martens, Benjamin P. Hershberg, Jan Craninckx:
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits 53(4): 1161-1171 (2018) - 2016
- [j7]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits 51(12): 3078-3092 (2016) - 2015
- [j6]Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx:
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. IEEE J. Solid State Circuits 50(5): 1203-1213 (2015) - 2014
- [j5]Skyler Weaver, Benjamin P. Hershberg, Un-Ku Moon:
Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 84-91 (2014) - 2012
- [j4]Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
Ring Amplifiers for Switched Capacitor Circuits. IEEE J. Solid State Circuits 47(12): 2928-2942 (2012) - 2011
- [j3]Skyler Weaver, Benjamin P. Hershberg, Nima Maghari, Un-Ku Moon:
Domino-Logic-Based ADC for Digital Synthesis. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 744-747 (2011) - 2010
- [j2]Benjamin P. Hershberg, Skyler Weaver, Un-Ku Moon:
Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp. IEEE J. Solid State Circuits 45(12): 2623-2633 (2010) - [j1]Skyler Weaver, Benjamin P. Hershberg, Peter Kurahashi, Daniel Knierim, Un-Ku Moon:
Stochastic Flash Analog-to-Digital Conversion. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(11): 2825-2833 (2010)
Conference and Workshop Papers
- 2023
- [c23]Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro:
A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. CICC 2023: 1-2 - 2021
- [c22]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC 2021: 207-210 - [c21]Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx:
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [c20]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits 2020: 1-2 - 2019
- [c19]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC 2019: 58-60 - [c18]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC 2019: 68-70 - 2018
- [c17]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC 2018: 1-4 - 2016
- [c16]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC 2016: 176-177 - [c15]Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx:
20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC 2016: 356-357 - 2015
- [c14]Tom Vermeulen, Barend van Liempd, Benjamin P. Hershberg, Sofie Pollin:
Real-time RF self-interference cancellation for in-band full duplex. DySPAN 2015: 275-276 - [c13]Björn Debaillie, Barend van Liempd, Benjamin P. Hershberg, Jan Craninckx, Kari Rikkinen, D. J. van den Broek, Eric A. M. Klumperink, Bram Nauta:
In-band full-duplex transceiver technology for 5G mobile networks. ESSCIRC 2015: 84-87 - [c12]Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx:
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC 2015: 176-179 - [c11]Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx:
2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. ISSCC 2015: 1-3 - 2014
- [c10]Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx:
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. ESSCIRC 2014: 83-86 - 2013
- [c9]Hariprasath Venkatram, Benjamin P. Hershberg, Taehwan Oh, Manideep Gande, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
Parallel gain enhancement technique for switched-capacitor circuits. CICC 2013: 1-4 - 2012
- [c8]Benjamin P. Hershberg, Tawfiq Musah, Skyler Weaver, Un-Ku Moon:
The effect of correlated level shifting on noise performance in switched capacitor circuits. ISCAS 2012: 942-945 - [c7]Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
Ring amplifiers for switched-capacitor circuits. ISSCC 2012: 460-462 - [c6]Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. VLSIC 2012: 32-33 - 2011
- [c5]Benjamin P. Hershberg, Skyler Weaver, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon:
Binary Access Memory: An optimized lookup table for successive approximation applications. ISCAS 2011: 1620-1623 - 2010
- [c4]Skyler Weaver, Benjamin P. Hershberg, Un-Ku Moon:
PDF folding for stochastic flash ADCs. ICECS 2010: 770-773 - [c3]Hariprasath Venkatram, Benjamin P. Hershberg, Un-Ku Moon:
Asynchronous CLS for Zero Crossing based Circuits. ICECS 2010: 1025-1028 - [c2]Benjamin P. Hershberg, Skyler Weaver, Un-Ku Moon:
A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp. ISSCC 2010: 302-303 - 2009
- [c1]Skyler Weaver, Benjamin P. Hershberg, Pavan Kumar Hanumolu, Un-Ku Moon:
A multiplexer-based digital passive linear counter (PLINCO). ICECS 2009: 607-610
Coauthor Index
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last updated on 2024-10-07 22:08 CEST by the dblp team
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