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ORCIDBidyut K. Bhattacharyya
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2020 – today
- 2024
[j24]Anirban Tarafdar
, Azharuddin Sheikh, Pinki Majumder, Abhijit Baidya, Alak Majumder, Bidyut K. Bhattacharyya, Uttam Kumar Bera:
Enhancing intrusion detection using wireless sensor networks: A novel ahp-madm aggregated multiple type 3 fuzzy logic-based k-barriers prediction system. Peer Peer Netw. Appl. 17(3): 1732-1749 (2024)- [c4]Sushmita Ghosh, Bidyut K. Bhattacharyya:
A Novel Approach to Control a DC-DC Converter Using its Empirical Physical Model. VLSID 2024: 637-642 - 2022
- [j23]Mili Dhar, Arindam Debnath, Bidyut K. Bhattacharyya, Mrinal Kanti Debbarma, Swapan Debbarma:
A comprehensive study of different objectives and solutions of controller placement problem in software-defined networks. Trans. Emerg. Telecommun. Technol. 33(5) (2022) - [j22]Mili Dhar, Bidyut K. Bhattacharyya, Mrinal Kanti Debbarma, Swapan Debbarma:
A cost-effective and load-balanced controller placement method in software-defined networks. Int. J. Netw. Manag. 32(5) (2022) - [j21]Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya:
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. Integr. 87: 364-377 (2022) - [j20]Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder:
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1704-1715 (2022) - 2021
- [j19]Sambit Satpathy, Bidyut K. Bhattacharyya, Munesh Chandra Trivedi, Aditya Sankar Sengupta:
Buck Topology Powered Exclusively by Supercapacitor Modules - A Battery-Less Design Concept. IEEE Access 9: 25758-25767 (2021) - [j18]Arindam Debnath, Habila Basumatary, Mili Dhar, Mrinal Kanti Debbarma, Bidyut K. Bhattacharyya:
Fuzzy logic-based VANET routing method to increase the QoS by considering the dynamic nature of vehicles. Computing 103(7): 1391-1415 (2021) - [j17]Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder:
A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst. Signal Process. 40(4): 1569-1588 (2021) - [j16]Mili Dhar, Bidyut K. Bhattacharyya, Mrinal Kanti Debbarma, Swapan Debbarma:
A new optimization technique to solve the latency aware controller placement problem in software defined networks. Trans. Emerg. Telecommun. Technol. 32(10) (2021) - [j15]Anirban Tarafdar, Abir J. Mondal, Uttam Kumar Bera, Bidyut K. Bhattacharyya:
A PVT aware differential delay circuit and its performance variation due to power supply noise. Integr. 76: 159-171 (2021) - [j14]Habila Basumatary, Arindam Debnath, Mrinal Kanti Debbarma, Bidyut Kumar Bhattacharyya:
Centroid-Based Routing protocol with moving sink node for uniform and non-uniform distribution of wireless sensor nodes. J. Supercomput. 77(4): 3727-3751 (2021) - [j13]Habila Basumatary, Arindam Debnath, MrinalKanti Deb Barma, Bidyut Kumar Bhattacharyya:
Clustering Based Two Dimensional Motion of Sink Node in Wireless Sensor Networks. Wirel. Pers. Commun. 118(1): 161-183 (2021) - 2020
- [j12]Kuldip Acharya, Dibyendu Ghoshal, Bidyut K. Bhattacharyya:
Segmentation of images through curve fitting analysis by modified Vandermonde matrix and modified Gram-Schmidt method. IET Image Process. 14(17): 4588-4598 (2020) - [j11]Madhusudan Maiti, Alak Majumder, Shubhro Chakrabartty, Hanjung Song, Bidyut K. Bhattacharyya:
Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range. Microelectron. J. 98: 104752 (2020) - [c3]Madhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder:
A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range. NorCAS 2020: 1-5
2010 – 2019
- 2019
- [j10]Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya:
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1231-1244 (2019) - 2018
- [j9]Aditya Sankar Sengupta, Sambit Satpathy, Saraju P. Mohanty, Debasis Baral, Bidyut K. Bhattacharyya:
Supercapacitors Outperform Conventional Batteries [Energy and Security]. IEEE Consumer Electron. Mag. 7(5): 50-53 (2018) - [j8]Abhisek Paul, Paritosh Bhattacharya, Santi P. Maity, Bidyut K. Bhattacharyya:
Plateau limit-based tri-histogram equalisation for image enhancement. IET Image Process. 12(9): 1617-1625 (2018) - [j7]Nivedita Laskar, Suman Debnath, Alak Majumder, Bidyut K. Bhattacharyya:
A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. J. Circuits Syst. Comput. 27(3): 1850049:1-1850049:20 (2018) - 2017
- [j6]Shirsha Ghosh, Alak Majumder, Joyeeta Goswami, Abhishek Kumar, Saraju P. Mohanty, Bidyut K. Bhattacharyya:
Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment. IEEE Consumer Electron. Mag. 6(1): 82-93 (2017) - [j5]Alak Majumder, Joyeeta Goswami, Shirsha Ghosh, Rishu Shrivastawa, Saraju P. Mohanty, Bidyut K. Bhattacharyya:
Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users. IEEE Consumer Electron. Mag. 6(2): 78-88 (2017) - [j4]Alak Majumder, Bidyut K. Bhattacharyya:
Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect. Turkish J. Electr. Eng. Comput. Sci. 25: 2055-2065 (2017) - [j3]Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. Integr. 58: 348-355 (2017) - [j2]Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya:
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. Integr. 58: 356-368 (2017) - [j1]Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
A 65 nm Design of 0.6 V/8.98 μW Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications. J. Low Power Electron. 13(3): 511-519 (2017) - [c2]Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya:
A Design Methodology for MOS Current Mode Logic VCO. iNIS 2017: 206-209 - [c1]Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS 2017: 210-214
Coauthor Index
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last updated on 2024-10-07 02:29 CEST by the dblp team
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