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Sunil R. Das
Person information
- affiliation: University of Ottawa, Canada
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2020 – today
- 2022
- [c29]William Sukaria, James Malasa, Shiu Kumar, Rahul Kumar, Mansour H. Assaf, Voicu Groza, Emil M. Petriu, Sunil R. Das:
Epileptic Seizure Detection Using Convolution Neural Networks. MeMeA 2022: 1-5 - 2021
- [c28]Komal Chand, Kavilash Chand, Rahul Kumar, Bibhya Sharma, Mansour H. Assaf, Sunil R. Das, Voicu Groza, Emil M. Petriu, Satyendra N. Biswas:
An Optimized Tongue Drive System for Disabled Persons. I2MTC 2021: 1-6
2010 – 2019
- 2019
- [j48]Samrat Pundalik Khadilkar, Sunil R. Das, Mansour H. Assaf, Satyendra N. Biswas:
Face Identification Based on Discrete Wavelet Transform and Neural Networks. Int. J. Image Graph. 19(4): 1950022:1-1950022:20 (2019) - 2018
- [j47]Mohammad Nazmus Sakib, Rakibul Hassan, Satyendra N. Biswas, Sunil R. Das:
Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1037-1049 (2018) - 2016
- [c27]Ezekiel Bokolonga, Martin Hauhana, Nicholas Rollings, David Aitchison, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Voicu Groza, Emil M. Petriu:
A compact multispectral image capture unit for deployment on drones. I2MTC 2016: 1-5 - [c26]Sunil R. Das, Abdullah-Al Amin, Satyendra N. Biswas, Mansour H. Assaf, Emil M. Petriu, Voicu Groza:
An algorithm for generating prime implicants. I2MTC 2016: 1-6 - [c25]Satyanand Singh, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Emil M. Petriu, Voicu Groza:
Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm. I2MTC 2016: 1-6 - 2015
- [c24]Amit Krishan Kumar, Mansour H. Assaf, Sunil R. Das, Satyendra N. Biswas, Emil M. Petriu, Voicu Groza:
Image processing based system for classification of vehicles for parking purposes. I2MTC 2015: 1326-1330 - [c23]Nicholas A. Malan, Sunil R. Das, Satyendra N. Biswas, Mansour H. Assaf, Scott Morton, Emil M. Petriu, Voicu Groza:
Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations. I2MTC 2015: 1408-1413 - 2014
- [j46]Satyendra N. Biswas, Sunil R. Das, Emil M. Petriu:
On System-on-Chip Testing Using Hybrid Test Vector Compression. IEEE Trans. Instrum. Meas. 63(11): 2611-2619 (2014) - [c22]Shashisekhar Ramagundam, Sunil R. Das, Scott Morton, Satyendra N. Biswas, Voicu Groza, Mansour H. Assaf, Emil M. Petriu:
Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture. I2MTC 2014: 10-15 - 2013
- [c21]Sunil R. Das, Danny L. Shaw, Satyendra N. Biswas, Mansour H. Assaf, Scott Morton, Irem Ozkarahan, Emil M. Petriu, Voicu Groza:
Data compression using mixed cascade of nonlinear logic. I2MTC 2013: 1544-1549 - [c20]Satyendra N. Biswas, Touhidul Hasan, Shuvashis DasGupta, Sunil R. Das, Voicu Groza, Emil M. Petriu, Mansour H. Assaf:
Compressed video watermarking technique. I2MTC 2013: 1790-1794 - 2011
- [c19]Altaf Hossain, Voicu Groza, Sunil R. Das:
Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic. DELTA 2011: 275-280
2000 – 2009
- 2008
- [j45]Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu:
Aliasing-free compaction revisited. IET Circuits Devices Syst. 2(1): 166-178 (2008) - [j44]Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu:
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. IEEE Trans. Instrum. Meas. 57(10): 2146-2168 (2008) - [c18]Satyendra N. Biswas, Sunil R. Das, Mansour H. Assaf:
A Novel Technique for Input Vector Compression in System-on-Chip Testing. ICIT 2008: 53-58 - 2007
- [j43]Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu:
Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach. IEEE Trans. Instrum. Meas. 56(3): 840-855 (2007) - 2006
- [j42]Sunil R. Das, Rochit Rajsuman:
Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. 55(2): 378-380 (2006) - [j41]Satyendra Biswas, Sunil R. Das, Emil M. Petriu:
Space compactor design in VLSI circuits based on graph theoretic concepts. IEEE Trans. Instrum. Meas. 55(4): 1106-1118 (2006) - [j40]Jianxun Liu, Wen-Ben Jone, Sunil R. Das:
Crosstalk test pattern generation for dynamic programmable logic arrays. IEEE Trans. Instrum. Meas. 55(4): 1288-1302 (2006) - 2005
- [j39]Sunil R. Das:
Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware. IEEE Trans. Instrum. Meas. 54(3): 941-955 (2005) - [j38]Mehmet Sahinoglu, David L. Libby, Sunil R. Das:
Measuring availability indexes with small samples for component and network reliability using the Sahinoglu-Libby probability model. IEEE Trans. Instrum. Meas. 54(3): 1283-1295 (2005) - [j37]Sunil R. Das, Rochit Rajsuman:
Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test. IEEE Trans. Instrum. Meas. 54(5): 1659-1661 (2005) - [j36]Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu:
Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization. IEEE Trans. Instrum. Meas. 54(5): 1662-1677 (2005) - [j35]Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das:
A built-in self-testing method for embedded multiport memory arrays. IEEE Trans. Instrum. Meas. 54(5): 1721-1738 (2005) - [j34]Satyendra Biswas, Sunil R. Das, Emil M. Petriu:
An adaptive compressed MPEG-2 video watermarking scheme. IEEE Trans. Instrum. Meas. 54(5): 1853-1861 (2005) - [j33]Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu:
Fault simulation and response compaction in full scan circuits using HOPE. IEEE Trans. Instrum. Meas. 54(6): 2310-2328 (2005) - 2004
- [j32]Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu:
Aliasing-Free Compaction in Testing Cores-Based System-on-Chip (SoC) using Compatibility of Response Data outputs. Trans. SDPS 8(1): 1-17 (2004) - [j31]Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das:
A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 53(4): 915-932 (2004) - [j30]Emil M. Petriu, Stephen K. S. Yeung, Sunil R. Das, Ana-Maria Cretu, Hans J. W. Spoelder:
Robotic tactile recognition of pseudorandom encoded objects. IEEE Trans. Instrum. Meas. 53(5): 1425-1432 (2004) - [c17]Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza, Mehmet Sahinoglu:
Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment. CIT 2004: 315-325 - [c16]Mansour H. Assaf, Sunil R. Das, Emil M. Petriu, Mehmet Sahinoglu:
Enhancing Testability in Architectural Design for the New Generation of Core-Based Embedded Systems. HASE 2004: 312-313 - [c15]Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu:
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. IWDC 2004: 353-360 - 2003
- [j29]Emil M. Petriu, Lichen Zhao, Sunil R. Das, Voicu Z. Groza, Aurel Cornell:
Instrumentation applications of multibit random-data representation. IEEE Trans. Instrum. Meas. 52(1): 175-181 (2003) - [j28]Sunil R. Das, Rochit Rajsuman:
Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)]. IEEE Trans. Instrum. Meas. 52(5): 1350-1352 (2003) - [j27]Sunil R. Das, Made Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu:
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. IEEE Trans. Instrum. Meas. 52(5): 1363-1380 (2003) - [j26]Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das:
An efficient BIST method for non-traditional faults of embedded memory arrays. IEEE Trans. Instrum. Meas. 52(5): 1381-1390 (2003) - [c14]Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza:
JBits Implementation and Design Verification in Space Compressor Design of Digital Circuits. Modelling, Identification and Control 2003: 415-420 - 2002
- [j25]Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Krishnendu Chakrabarty:
Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering. IEEE Trans. Instrum. Meas. 51(1): 150-172 (2002) - [c13]Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Sujoy Mukherjee:
Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability. IWDC 2002: 234-245 - 2001
- [j24]Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das:
An adaptive path selection method for delay testing. IEEE Trans. Instrum. Meas. 50(5): 1109-1118 (2001) - [j23]Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone:
Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities. IEEE Trans. Instrum. Meas. 50(6): 1725-1747 (2001) - [j22]Sunil R. Das:
Guest Editorial. VLSI Design 12(4) (2001) - [j21]Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das:
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. VLSI Design 12(4): 457-474 (2001) - [j20]Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das:
Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design 12(4): 537-549 (2001) - [c12]Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. VLSI Design 2001: 379-384 - [c11]Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. VLSI Design 2001: 397-402 - 2000
- [j19]Krishnendu Chakrabarty, Sunil R. Das:
Test-set embedding based on width compression for mixed-mode BIST. IEEE Trans. Instrum. Meas. 49(3): 671-678 (2000) - [j18]Sunil R. Das, Tony F. Barakat, Emil M. Petriu, Mansour H. Assaf, Krishnendu Chakrabarty:
Space compression revisited. IEEE Trans. Instrum. Meas. 49(3): 690-705 (2000)
1990 – 1999
- 1998
- [j17]Sunil R. Das, Emil M. Petriu, Tony F. Barakat, Mansour H. Assaf, Amiya R. Nayak:
Space compaction under generalized mergeability. IEEE Trans. Instrum. Meas. 47(5): 1283-1293 (1998) - [j16]Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak:
Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. VLSI Design 7(2): 191-201 (1998) - [c10]Emil M. Petriu, Sunil R. Das, Niculaie Trif, Stephen S. K. Yeung:
Pseudorandom encoding for structured light applications. CATA 1998: 287-290 - [c9]Wen-Ben Jone, Sunil R. Das:
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. VLSI Design 1998: 382- - 1997
- [j15]Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das:
Delay Fault Coverage Enhancement Using Variable Observation Times. J. Electron. Test. 11(2): 131-146 (1997) - [c8]Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das:
Delay Fault Coverage Enhancement Using Multiple Test Observation Times. VLSI Design 1997: 106-110 - 1996
- [j14]Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das:
PGEN: A Novel Approach to Sequential Circuit Test Generation. VLSI Design 4(3): 149-165 (1996) - [j13]Sunil R. Das:
Guest Editorial. VLSI Design 4(3): i-iv (1996) - [c7]Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak:
Syndrome signature in output compaction for VLSI BIST. VLSI Design 1996: 337-338 - 1995
- [j12]Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak, Ian Choi:
On testing of sequential machines using circuit decomposition and stochastic modeling. IEEE Trans. Syst. Man Cybern. 25(3): 489-504 (1995) - [j11]Wen-Ben Jone, Sunil R. Das:
CACOP-a random pattern testability analyzer. IEEE Trans. Syst. Man Cybern. 25(5): 865-871 (1995) - [c6]Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak:
An improved output compaction technique for built-in self-test in VLSI circuits. VLSI Design 1995: 403-407 - 1994
- [c5]Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das:
Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. ICPADS 1994: 360-365 - [c4]Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi:
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. VLSI Design 1994: 311-314 - 1993
- [j10]Sunil R. Das:
Guest Editorial. VLSI Design 1(1): iii-iv (1993) - [c3]Wen-Ben Jone, Sunil R. Das:
CACOP - A Random Pattern Testability Analyzer. VLSI Design 1993: 61-64 - 1992
- [j9]Sunil R. Das, Wen-Ben Jone:
On random testing for combinational circuits with a high measure of confidence. IEEE Trans. Syst. Man Cybern. 22(4): 748-754 (1992) - 1990
- [j8]Wen-Ben Jone, Sunil R. Das:
Multiple-output parity bit signature for exhaustive testing. J. Electron. Test. 1(2): 175-178 (1990) - [j7]Sunil R. Das, Wen-Ben Jone, K. L. Wong:
Probabilistic modeling and fault analysis in sequential logic using computer simulation. IEEE Trans. Syst. Man Cybern. 20(2): 490-498 (1990) - [c2]Sunil R. Das, Amiya Nayak:
A survey on bit dimension optimization strategies of microprograms. MICRO 1990: 281-291
1980 – 1989
- 1987
- [j6]Sunil R. Das, Ping Chao, Zen Chen, Yow Lung Dai, Mrinal K. Das:
Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices. Comput. Oper. Res. 14(5): 415-433 (1987) - 1986
- [j5]Sunil R. Das, S. Y. Lee:
An appraisal of the performance of the MMSC subgraph generation algorithm on a Cyber System 170/720. Computing 37(4): 365-370 (1986) - [c1]Sunil R. Das:
On random testing of sequential digital logic with a high confidence measure (abstract). ACM Conference on Computer Science 1986: 498
1970 – 1979
- 1979
- [j4]Sunil R. Das, C. L. Sheng, Zen Chen, W. J. Hsu:
Transition matrices in the measurement and control of synchronous sequential machines. Inf. Sci. 18(1): 47-65 (1979) - 1978
- [j3]Sunil R. Das, C. L. Sheng:
Strong connectivity in symmetric graphs and generation of maximal minimally strongly connected subgraphs. Inf. Sci. 14(3): 181-187 (1978) - 1973
- [j2]N. S. Khabra, Sunil R. Das:
Multiform Partial Symmetry and Linearity. IEEE Trans. Computers 22(8): 804 (1973) - 1972
- [j1]Sunil R. Das, Narinder Singh Khabra:
Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions. IEEE Trans. Computers 21(11): 1239-1246 (1972)
Coauthor Index
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