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Vinay B. Y. Kumar
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2020 – today
- 2022
- [j3]Simei Yang
, Debjyoti Bhattacharjee
, Vinay B. Y. Kumar
, Saikat Chatterjee, Sayandip De, Peter Debacker
, Diederik Verkest, Arindam Mallik, Francky Catthoor:
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 508-521 (2022) - 2021
- [c14]Anubhab Baksi, Shivam Bhasin, Jakub Breier
, Anupam Chattopadhyay, Vinay B. Y. Kumar
:
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks. DATE 2021: 561-564 - 2020
- [j2]Vinay B. Y. Kumar
, Suman Deb, Naina Gupta, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson:
Towards Designing a Secure RISC-V System-on-Chip: ITUS. J. Hardw. Syst. Secur. 4(4): 329-342 (2020) - [c13]Anubhab Baksi, Vinay B. Y. Kumar
, Banashri Karmakar
, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay:
A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis. ACISP 2020: 525-542 - [c12]Vinay B. Y. Kumar
, Naina Gupta, Anupam Chattopadhyay, Michael Kasper, Christoph Krauß
, Ruben Niederhagen:
Post-Quantum Secure Boot. DATE 2020: 1582-1585 - [c11]Shivam Bhasin, Trevor E. Carlson, Anupam Chattopadhyay, Vinay B. Y. Kumar, Avi Mendelson, Romain Poussier, Yaswanth Tavva:
Secure Your SoC: Building System-an-Chip Designs for Security. SoCC 2020: 248-253 - [i3]Anubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay:
A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis. IACR Cryptol. ePrint Arch. 2020: 1268 (2020) - [i2]Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar:
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version). IACR Cryptol. ePrint Arch. 2020: 1542 (2020)
2010 – 2019
- 2019
- [c10]Vinay B. Y. Kumar
, Suman Deb, Rupesh Kumar
, Mustafa Khairallah
, Anupam Chattopadhyay, Avi Mendelson:
Recruiting Fault Tolerance Techniques for Microprocessor Security. ATS 2019: 80-85 - [c9]Vinay B. Y. Kumar
, Anupam Chattopadhyay, Jawad Haj-Yahya, Avi Mendelson:
ITUS: A Secure RISC-V System-on-Chip. SoCC 2019: 418-423 - 2018
- [c8]Vinay B. Y. Kumar
, Deval Shah, Mandar Datar, Sachin B. Patkar:
Lightweight Forth Programmable NoCs. VLSID 2018: 368-373 - 2016
- [c7]Vinay B. Y. Kumar
, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar:
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. VLSID 2016: 409-414 - 2015
- [c6]Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar
, Gaurav Trivedi, Sachin B. Patkar:
Parallel two step random walk algorithm to analyze VLSI power grid networks. VDAT 2015: 1-2 - [i1]Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar:
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies. CoRR abs/1508.06823 (2015) - 2014
- [c5]Vinay B. Y. Kumar
, Shovan Maity, Sachin B. Patkar:
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping. ICCD 2014: 464-469 - [c4]Vivek Kumar, Vinay B. Y. Kumar
, Sachin B. Patkar:
FPGA-based implementation of M4RM for matrix multiplication over GF(2). VDAT 2014: 1-2 - [c3]Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar
, Sachin B. Patkar:
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems. VLSI-DAT 2014: 1-4 - 2013
- [c2]Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar:
Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields. PECCS 2013: 195-201 - 2010
- [j1]Vinay B. Y. Kumar
, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. Int. J. Parallel Program. 38(3-4): 322-338 (2010)
2000 – 2009
- 2009
- [c1]Vinay B. Y. Kumar
, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. VLSI Design 2009: 341-346
Coauthor Index
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last updated on 2024-05-08 21:44 CEST by the dblp team
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