"Apply high-level synthesis design and verification methodology on ..."

Chia-I Chen et al. (2014)

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DOI: 10.1109/VLSI-DAT.2014.6834921

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu:
Apply high-level synthesis design and verification methodology on floating-point unit implementation. VLSI-DAT 2014: 1-4

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