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ORCID"Saving 78.11% Dhrystone power consumption in FPU by clock gating while ..."
Minh Thien Trieu et al. (2011)
- Minh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama:
Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU. ASICON 2011: 39-42
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