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ORCIDValentin Gherman
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Journal Articles
- 2024
[j5]Bastien Giraud
, Sebastien Ricavy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Olivier Guille, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noel, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas:
Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. IEEE J. Solid State Circuits 59(9): 3045-3057 (2024)- 2020
- [j4]Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman:
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. 36(1): 33-46 (2020) - 2014
- [j3]Samuel Evain, Valentin Savin, Valentin Gherman:
Error Correction Schemes with Erasure Information for Fast Memories. J. Electron. Test. 30(2): 183-192 (2014) - 2013
- [j2]Valentin Gherman, Samuel Evain, Yannick Bonhomme:
Memory Reliability Improvement Based on Maximized Error-Correcting Codes. J. Electron. Test. 29(4): 601-608 (2013) - 2007
- [j1]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers:
Deterministic logic BIST for transition fault testing. IET Comput. Digit. Tech. 1(3): 180-186 (2007)
Conference and Workshop Papers
- 2024
- [c21]Valentin Gherman, Cyrille Laffond:
Sequential Decoders for Binary Linear Block ECCs. VTS 2024: 1-5 - 2023
- [c20]Bastien Giraud, Sebastien Ricavy, Yasser Moursy, Cyrille Laffond, Ilan Sever, Valentin Gherman, Manuel Pezzin, Florent Lepin, Mariam Diallo, Khadija Zenati, Sylvain Dumas, Maxim Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, Anass Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas:
Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. IMW 2023: 1-4 - 2020
- [c19]Valentin Gherman, Samuel Evain, Bastien Giraud:
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. DATE 2020: 298-301 - 2018
- [c18]Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman:
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS 2018: 1-6 - [c17]Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo:
Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells. DTIS 2018: 1-5 - 2017
- [c16]Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman:
Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. ETS 2017: 1-6 - [c15]Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo:
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. ITC 2017: 1-9 - 2014
- [c14]Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman:
Shadow-scan design with low latency overhead and in-situ slack-time monitoring. ETS 2014: 1-6 - [c13]Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman:
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. IOLTS 2014: 160-163 - 2013
- [c12]Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman:
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. DATE 2013: 1077-1082 - [c11]Samuel Evain, Valentin Gherman:
Error-correction schemes with erasure information for fast memories. ETS 2013: 1-6 - 2012
- [c10]Valentin Gherman, Samuel Evain, Yannick Bonhomme:
Memory reliability improvements based on maximized error-correcting codes. ETS 2012: 1-6 - 2011
- [c9]Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme:
Error prediction based on concurrent self-test and reduced slack time. DATE 2011: 1626-1631 - [c8]Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme:
Generalized parity-check matrices for SEC-DED codes with fixed parity. IOLTS 2011: 198-201 - [c7]Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme:
Programmable extended SEC-DED codes for memory errors. VTS 2011: 140-145 - 2010
- [c6]Samuel Evain, Yannick Bonhomme, Valentin Gherman:
Programmable restricted SEC codes to mask permanent faults in semiconductor memories. IOLTS 2010: 147-153 - 2009
- [c5]Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme:
System-level hardware-based protection of memories against soft-errors. DATE 2009: 1222-1225 - 2007
- [c4]Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers:
Synthesis of irregular combinational functions with large don't care sets. ACM Great Lakes Symposium on VLSI 2007: 287-292 - 2006
- [c3]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers:
Deterministic Logic BIST for Transition Fault Testing. ETS 2006: 123-130 - 2005
- [c2]Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel:
Implementing a Scheme for External Deterministic Self-Test. VTS 2005: 101-106 - 2004
- [c1]Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers:
Efficient Pattern Mapping for Deterministic Logic BIST. ITC 2004: 48-56
Coauthor Index
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