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ORCID20th IOLTS 2014: Platja d'Aro, Girona, Spain
- 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014. IEEE 2014, ISBN 978-1-4799-5323-3
- Gulay Yalcin, Emrah Islek, Oyku Tozlu, Pedro Reviriego
, Adrián Cristal, Osman S. Unsal, Oguz Ergin:
Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches. 1-6 - Arwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner:
Comparative study of defect-tolerant multiplexers for FPGAs. 7-12 - Tiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe Maia Galvão França:
Online error detection and recovery in dataflow execution. 9-12 - Atefe Dalirsani, Michael A. Kochte, Hans-Joachim Wunderlich:
Area-efficient synthesis of fault-secure NoC switches. 13-18 - Nasim Pour Aryan, A. Listl, Leonhard Heiß, Cenk Yilmaz, Georg Georgakos, Doris Schmitt-Landsiedel:
From an analytic NBTI device model to reliability assessment of complex digital circuits. 19-24 - Álvaro Gómez-Pau, Suvadeep Banerjee, Abhijit Chatterjee:
Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksums. 25-30 - Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
Pre-bond testing of weak defects in TSVs. 31-36 - Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Customized cell detector for laser-induced-fault detection. 37-42 - Raghavan Kumar, Philipp Jovanovic, Ilia Polian:
Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. 43-48 - Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. 49-54 - Yukiya Miura, Yoshihiro Ohkawa:
A noise-tolerant master-slave flip-flop. 55-61 - Hao Xie, Li Chen, Rui Liu, Adrian Evans, Dan Alexandrescu, Shi-Jie Wen, Rick Wong:
New approaches for synthesis of redundant combinatorial logic for selective fault tolerance. 62-68 - Samuel N. Pagliarini, Dhiraj K. Pradhan:
A placement strategy for reducing the effects of multiple faults in digital circuits. 69-74 - Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel:
Cost-efficient of a cluster in a mesh SRAM-based FPGA. 75-80 - Michael Frischke, Andreas J. Rohatschek, Walter Stechele:
Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems. 81-86 - Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Alessandro Vallero:
A novel methodology to increase fault tolerance in autonomous FPGA-based systems. 87-92 - Milos Krstic, Stefan Weidling, Vladimir Petrovic, Michael Gössel:
Improved circuitry for soft error correction in combinational logic in pipelined designs. 93-98 - Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
A new solution to on-line detection of Control Flow Errors. 105-110 - Marco Desogus, Luca Sterpone, David Merodio Codinachs:
Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs. 111-115 - Christian Badack, Thomas Kern, Michael Gössel:
Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors. 116-121 - Katerina Katsarou, Yiorgos Tsiatouhas:
Double node charge sharing SEU tolerant latch design. 122-127 - David May, Walter Stechele:
Improving the significance of probabilistic circuit fault emulations. 128-133 - Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas:
Error masking with approximate logic circuits using dynamic probability estimations. 134-139 - Nikos Foutris, Manolis Kaliorakis, Sotiris Tselonis, Dimitris Gizopoulos:
Versatile architecture-level fault injection framework for reliability evaluation: A first report. 140-145 - Gaurang Upasani, Xavier Vera, Antonio González:
Framework for economical error recovery in embedded cores. 146-153 - George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
Power-aware optimization of software-based self-test for L1 caches in microprocessors. 154-159 - Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman:
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. 160-163 - Jeff Tikkanen, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir:
Multivariate outlier modeling for capturing customer returns - How simple it can be. 164-169 - Kim Petersén, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson, Farrokh Ghani Zadegan, Erik Larsson:
Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687. 170-175 - Anna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda:
Permanent faults on LIN networks: On-line test generation. 176-181 - Samuel N. Pagliarini, Lirida A. B. Naviner, Jean-François Naviner, Dhiraj K. Pradhan:
A hybrid reliability assessment method and its support of sequential logic modelling. 182-183 - Phaninder Alladi, Spyros Tragoudas:
Aging-aware critical paths in deep submicron. 184-185 - Luca Cassano, Hipólito Guzmán-Miranda, Miguel A. Aguirre:
Early assessment of SEU sensitivity through untestable fault identification. 186-189 - Sebastian Müller, Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus:
Timing for virtual TMR in logic circuits. 190-193 - Vanessa Vargas, Pablo Ramos, Wassim Mansour, Raoul Velazco, Nacer-Eddine Zergainoh, Jean-François Méhaut:
Preliminary results of SEU fault-injection on multicore processors in AMP mode. 194-197 - Prakash Narayanan, Satish Ravichandran, Balaji Ramayanam:
Novel self-test methods to reduce on-chip memory requirements and improved test coverage. 198-199 - Nicholas Axelos, Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs. 200-201 - Honorio Martín, Anna Vaskova, Celia López-Ongil, Enrique San Millán, Marta Portela-García:
Effect of ionizing radiation on TRNGs for safe telecommunications: Robustness and randomness. 202-205 - Loic Welter, Philippe Dreux, Hassen Aziza, Jean-Michel Portal:
An innovative standard cells remapping method for in-circuit critical parameters monitoring. 206-209 - M. De Carvalho, Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro:
Fault injection in GPGPU cores to validate and debug robust parallel applications. 210-211 - Christelle Hobeika, Simon Pichette, M. A. Leonard, Claude Thibeault, Jean-François Boland, Yves Audet:
Multi-abstraction level signature generation and comparison based on radiation single event upset. 212-215 - Dan Alexandrescu, Nematollah Bidokhti, Andy Yu, Adrian Evans, Enrico Costenaro:
Managing SER costs of complex systems through Linear Programming. 216-219 - Wassim Mansour, Miguel A. Aguirre, Hipólito Guzmán-Miranda, Javier Barrientos Rojas, Raoul Velazco:
Two complementary approaches for studying the effects of SEUs on HDL-based designs. 220-221 - Antonis M. Paschalis, Harald Michalik, Nektarios Kranitis, Celia López-Ongil, Pedro Reviriego Vasallo:
Dependable reconfigurable space systems: Challenges, new trends and case studies. 222-227 - Stefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio González, Ramon Canal, Riccardo Mariani, M. Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenbach, Gulzaib Rafiq, Trond Loekstad:
Cross-layer early reliability evaluation: Challenges and promises. 228-233 - Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos:
Solutions for the self-adaptation of communicating systems in operation. 234-239
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