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ORCIDMatheus T. Moreira
Matheus Trevisan Moreira – Matheus Trevisan
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Books and Theses
- 2016
[b1]Matheus Trevisan Moreira:
Asynchronous circuits: innovations in components, cell libraries and design templates. Pontifícia Universidade Católica do Rio Grande do Sul, Brazil, 2016
Journal Articles
- 2021
- [j12]Leonardo Rezende Juracy
, Matheus Trevisan Moreira, Alexandre de Morais Amory, Alexandre F. Hampel, Fernando Gehm Moraes:
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4783-4795 (2021) - 2018
- [j11]Matheus T. Moreira, Peter A. Beerel, Marcos L. L. Sartori, Ney Laert Vilar Calazans:
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1981-1993 (2018) - [j10]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques:
Libra: An Automatic Design Methodology for CMOS Complex Gates. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1345-1349 (2018) - [j9]Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Alexandre M. Amory:
A DfT Insertion Methodology to Scannable Q-Flop Elements. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1609-1612 (2018) - 2017
- [j8]Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory:
Optimized Design of an LSSD Scan Cell. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 765-768 (2017) - 2016
- [j7]Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel:
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. ACM J. Emerg. Technol. Comput. Syst. 13(2): 15:1-15:23 (2016) - [j6]Sergio Johann Filho, Matheus T. Moreira, Leandro S. Heck, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel:
A processor for IoT applications: An assessment of design space and trade-offs. Microprocess. Microsystems 42: 156-164 (2016) - [j5]Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1188-1199 (2016) - [j4]Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel:
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 858-862 (2016) - 2015
- [j3]Matheus Trevisan Moreira, Michel Evandro Arendt, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Static Differential NCL Gates: Toward Low Power. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 563-567 (2015) - 2014
- [j2]Matheus Trevisan Moreira, Guilherme Trojan, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Spatially Distributed Dual-Spacer Null Convention Logic Design. J. Low Power Electron. 10(3): 313-320 (2014) - [j1]Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Beware the Dynamic C-Element. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1644-1647 (2014)
Conference and Workshop Papers
- 2024
- [c66]Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné:
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC 2024: 210-212 - 2023
- [c65]Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné:
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC 2023: 58-59 - [c64]Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. SBCCI 2023: 1-6 - 2021
- [c63]Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC 2021: 530-535 - [c62]Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC 2021: 859-864 - [c61]Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans:
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. ISCAS 2021: 1-5 - [c60]Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory, Fernando Gehm Moraes:
A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. LASCAS 2021: 1-4 - 2020
- [c59]Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans:
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. ASYNC 2020: 3-10 - [c58]Matheus Trevisan Moreira, Stefano Giaconi:
Chronos Link: A QDI Interconnect for Modern SoCs. ASYNC 2020: 67-68 - [c57]Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory:
Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template. ASYNC 2020: 86-93 - [c56]Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans:
Leveraging QDI Robustness to Simplify the Design of IoT Circuits. ISCAS 2020: 1-5 - 2019
- [c55]Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans:
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. ASYNC 2019: 114-123 - 2018
- [c54]Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory:
An LSSD Compliant Scan Cell for Flip-Flops. ISCAS 2018: 1-5 - [c53]Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory:
Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template. SBCCI 2018: 1-6 - 2017
- [c52]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
A post-processing methodology to improve the automatic design of CMOS gates at layout-level. ICECS 2017: 42-45 - [c51]Leandro S. Heck, Matheus T. Moreira, Ney Laert Vilar Calazans:
Hardening C-elements against metastability. ICECS 2017: 314-317 - [c50]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
Post-processing of supergate networks aiming cell layout optimization. ISCAS 2017: 1-4 - [c49]Ricardo A. Guazzelli, Matheus T. Moreira, Ney Laert Vilar Calazans:
A comparison of asynchronous QDI templates using static logic. LASCAS 2017: 1-4 - [c48]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Leomar S. da Rosa, Felipe de Souza Marques:
Transistor placement strategies for non-series-parallel cells. MWSCAS 2017: 523-526 - [c47]Felipe T. Bortolon, Fernando Gehm Moraes, Matheus T. Moreira, Sergio Bampi:
Estimation methods for static noise margins in CMOS subthreshold logic circuits. SBCCI 2017: 90-95 - [c46]Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
Sleep convention logic isochronic fork: an analysis. SBCCI 2017: 103-109 - 2016
- [c45]Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel:
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC 2016: 11-18 - [c44]Carlos Henrique Menezes Oliveira, Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans:
ASCEnD-FreePDK45: An open source standard cell library for asynchronous design. ICECS 2016: 652-655 - [c43]Sergio Johann Filho, Matheus T. Moreira, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel:
The HF-RISC processor: Performance assessment. LASCAS 2016: 95-98 - [c42]Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.:
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. LASCAS 2016: 355-358 - [c41]Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa:
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. MWSCAS 2016: 1-4 - [c40]Felipe Todeschini Bortolon, Sergio Johann Filho, Matheus Gibiluka, Sergio Bampi, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel, Matheus Trevisan Moreira:
Design and analysis of the HF-RISC processor targeting voltage scaling applications. SBCCI 2016: 1-6 - [c39]Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
A standard cell characterization flow for non-standard voltage supplies. SBCCI 2016: 1-6 - 2015
- [c38]Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Blade - A Timing Violation Resilient Asynchronous Template. ASYNC 2015: 21-28 - [c37]Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC 2015: 61-68 - [c36]Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Design and Analysis of Testable Mutual Exclusion Elements. ASYNC 2015: 124-131 - [c35]Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. DSD 2015: 79-86 - [c34]Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans:
TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED 2015: 379-383 - [c33]Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel:
A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. ISVLSI 2015: 27-32 - [c32]Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
BAT-Hermes: A transition-signaling bundled-data NoC router. LASCAS 2015: 1-4 - [c31]Guilherme Heck, Leandro S. Heck, Matheus T. Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. LASCAS 2015: 1-4 - [c30]Ricardo A. Guazzelli, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Matheus T. Moreira:
SDDS-NCL Design: Analysis of Supply Voltage Scaling. SBCCI 2015: 2:1-2:7 - [c29]Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans:
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. VLSID 2015: 321-326 - 2014
- [c28]Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans:
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC 2014: 53-60 - [c27]Matheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans:
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. ASYNC 2014: 93-100 - [c26]Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans:
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. ACM Great Lakes Symposium on VLSI 2014: 3-8 - [c25]Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans:
A design flow for physical synthesis of digital cells with ASTRAN. ACM Great Lakes Symposium on VLSI 2014: 245-246 - [c24]Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans:
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ISQED 2014: 692-699 - [c23]Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans:
Automatic layout synthesis with ASTRAN applied to asynchronous cells. LASCAS 2014: 1-4 - [c22]Ricardo A. Guazzelli, Guilherme Heck, Matheus T. Moreira, Ney Laert Vilar Calazans:
Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? LATW 2014: 1-5 - [c21]Matheus Trevisan, Michel Evandro Arendt, Adriel Ziesemer, Ricardo Augusto da Luz Reis, Ney Laert Vilar Calazans:
Automated Synthesis of Cell Libraries for Asynchronous Circuits. SBCCI 2014: 16:1-16:7 - [c20]Matheus T. Moreira, Ney Laert Vilar Calazans:
Advances on the state of the art in QDI design. VLSI-SoC 2014: 163-164 - 2013
- [c19]Matheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Charge sharing aware NCL gates design. DFTS 2013: 212-217 - [c18]Matheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost:
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. DSD 2013: 933-940 - [c17]Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
Voltage scaling on C-elements: A speed, power and energy efficiency analysis. ICCD 2013: 329-334 - [c16]Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski:
Evaluating the scalability of test buses. ISSoC 2013: 1-6 - [c15]Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. ISVLSI 2013: 217-218 - [c14]Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans:
Design of NCL gates with the ASCEnD flow. LASCAS 2013: 1-4 - [c13]Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans:
NCL+: Return-to-one Null Convention Logic. MWSCAS 2013: 836-839 - [c12]Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans:
BaBaNoC: An asynchronous network-on-chip described in Balsa. RSP 2013: 37-43 - [c11]Yan Ghidini, Matheus T. Moreira, Lucas Brahm, Thais Webber, Ney Calazans, César A. M. Marcon:
Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy. SBCCI 2013: 1-6 - 2012
- [c10]Fernando Gehm Moraes, Matheus T. Moreira, Carlos Lucas, D. Correa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans:
A generic FPGA emulation framework. ICECS 2012: 233-236 - [c9]Matheus T. Moreira, Ney Laert Vilar Calazans:
Electrical characterization of a C-Element with LiChEn. ICECS 2012: 583-585 - [c8]Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans:
Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits. ICECS 2012: 669-672 - [c7]Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans:
Impact of C-elements in asynchronous circuits. ISQED 2012: 437-343 - [c6]Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans:
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. SBCCI 2012: 1-6 - 2011
- [c5]Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans:
Adapting a C-element design flow for low power. ICECS 2011: 45-48 - [c4]Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans:
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC 2011: 99-104 - 2010
- [c3]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS 2010: 150-159 - [c2]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC 2010: 493-498 - 2008
- [c1]Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans:
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI 2008: 347-352
Informal and Other Publications
- 2020
- [i1]Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes:
A Survey of Aging Monitors and Reconfiguration Techniques. CoRR abs/2007.07829 (2020)
Coauthor Index
Ney Laert Vilar Calazans
aka: Ney Calazans
aka: Ney Calazans
[j11] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c64] [c61] [c59] [c56] [c55] [c51] [c49] [c46] [c45] [c44] [c43] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
Ricardo A. Guazzelli
aka: Ricardo Aquino Guazzelli
aka: Ricardo Aquino Guazzelli
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