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"A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in ..."

Ramy N. Tadros et al. (2016)

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DOI: 10.1109/TCSII.2016.2536179

access: closed

type: Journal Article

metadata version: 2022-10-02

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Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel:
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 858-862 (2016)

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