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Renato Souza de Souza
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2010 – 2019
- 2017
- [c4]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
A post-processing methodology to improve the automatic design of CMOS gates at layout-level. ICECS 2017: 42-45 - [c3]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
Post-processing of supergate networks aiming cell layout optimization. ISCAS 2017: 1-4 - 2016
- [c2]Maicon Schneider Cardoso, Regis Zanandrea, Renato Souza de Souza, Joao Junior da Silva Machado, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Topological characteristics of logic networks generated by a graph-based methodology. LASCAS 2016: 343-346 - [c1]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Regis Zanandrea, Renato Souza de Souza, Leomar S. da Rosa, Felipe de Souza Marques:
Physical design of supergate cells aiming geometrical optimizations. MWSCAS 2016: 1-4
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last updated on 2024-04-24 23:16 CEST by the dblp team
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