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ORCIDNaofumi Takagi
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2020 – today
- 2022
[j64]Takahiro Kawaguchi, Naofumi Takagi:
32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor. IEICE Trans. Electron. 105-C(6): 245-250 (2022)- 2021
- [c24]Ryota Miyagi, Naofumi Takagi, Sho Kinoshista, Masashi Oda, Hideki Takase:
Zytlebot : FPGA integrated ros-based autonomous mobile robot. FPT 2021: 1-4 - 2020
- [j63]Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
:
mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices. J. Inf. Process. 28: 150-160 (2020)
2010 – 2019
- 2019
- [j62]Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi:
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12: 78-80 (2019) - [j61]Nobutaka Kito, Naofumi Takagi:
Concurrent Error Detectable Carry Select Adder with Easy Testability. IEEE Trans. Computers 68(7): 1105-1110 (2019) - [c23]Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi:
mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices. HEART 2019: 7:1-7:6 - [e1]Naofumi Takagi, Sylvie Boldo, Martin Langhammer:
26th IEEE Symposium on Computer Arithmetic, ARITH 2019, Kyoto, Japan, June 10-12, 2019. IEEE 2019, ISBN 978-1-7281-3366-9 [contents] - 2018
- [j60]Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi:
Algorithms for Evaluating the Matrix Polynomial I+A+A2+...+AN-1 with Reduced Number of Matrix Multiplications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 467-471 (2018) - [c22]Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi:
Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress. EMSOFT 2018: 6 - 2017
- [j59]Naofumi Takagi:
Recap of the 22nd Asia and South- Pacific Design Automation Conference. IEEE Des. Test 34(3): 103-104 (2017) - [j58]Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi:
Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication. IEICE Trans. Inf. Syst. 100-D(3): 531-536 (2017) - 2016
- [j57]Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi:
RSFQ 4-bit Bit-Slice Integer Multiplier. IEICE Trans. Electron. 99-C(6): 697-702 (2016) - [j56]Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi:
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation. IEICE Trans. Electron. 99-C(6): 703-709 (2016) - [c21]Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi:
An evaluation framework of OS-level power managements for the big.LITTLE architecture. NEWCAS 2016: 1-4 - 2015
- [j55]Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi:
A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2556-2564 (2015) - [j54]Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. Inf. Media Technol. 10(3): 420-424 (2015) - [j53]Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 8: 100-104 (2015) - 2014
- [j52]Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi:
Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation. IEICE Trans. Electron. 97-C(3): 132-140 (2014) - [j51]Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa, Akira Fujimaki, Hiroyuki Akaike, Naofumi Takagi, Kazuaki J. Murakami:
A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits. IEICE Trans. Electron. 97-C(3): 141-148 (2014) - [j50]Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi:
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits. IEICE Trans. Electron. 97-C(3): 149-156 (2014) - [j49]Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi:
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors. IEICE Trans. Electron. 97-C(3): 157-165 (2014) - [j48]Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka:
Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process. IEICE Trans. Electron. 97-C(3): 188-193 (2014) - [j47]Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2498-2506 (2014) - [c20]Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. HPCC/CSS/ICESS 2014: 546-549 - 2013
- [j46]Nobutaka Kito, Naofumi Takagi:
Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication. IEICE Trans. Inf. Syst. 96-D(9): 1962-1970 (2013) - [c19]Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis. ICA3PP (1) 2013: 390-401 - 2012
- [j45]Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition. IEICE Trans. Electron. 95-C(4): 456-467 (2012) - [j44]Nobutaka Kito, Shinichi Fujii, Naofumi Takagi:
A C-Testable Multiple-Block Carry Select Adder. IEICE Trans. Inf. Syst. 95-D(4): 1084-1092 (2012) - [j43]Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi:
Fast inversion algorithm in GF(2m) suitable for implementation with a polynomial multiply instruction on GF(2). IET Comput. Digit. Tech. 6(3): 180-185 (2012) - 2011
- [j42]Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi:
Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits. IEICE Trans. Electron. 94-C(3): 288-295 (2011) - [j41]Hirotaka Kawashima, Naofumi Takagi:
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. Inf. Media Technol. 6(4): 1067-1075 (2011) - [j40]Hirotaka Kawashima, Naofumi Takagi:
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. IPSJ Trans. Syst. LSI Des. Methodol. 4: 131-139 (2011) - 2010
- [j39]Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing. IEICE Trans. Inf. Syst. 93-D(2): 300-305 (2010) - [j38]Naofumi Takagi, Masamitsu Tanaka:
Comparisons of Synchronous-Clocking SFQ Adders. IEICE Trans. Electron. 93-C(4): 429-434 (2010) - [j37]Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki:
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm. IEICE Trans. Electron. 93-C(4): 435-439 (2010) - [j36]Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka:
100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process. IEICE Trans. Electron. 93-C(4): 440-444 (2010) - [j35]Nobutaka Kito, Kensuke Hanai, Naofumi Takagi:
A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier. IEICE Trans. Inf. Syst. 93-D(10): 2783-2791 (2010)
2000 – 2009
- 2009
- [j34]Katsuki Kobayashi, Naofumi Takagi:
Fast Hardware Algorithm for Division in hbox 2m Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions. IEEE Trans. Circuits Syst. II Express Briefs 56-II(8): 644-648 (2009) - 2008
- [j33]Naofumi Takagi, Kazuaki J. Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda:
Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. IEICE Trans. Electron. 91-C(3): 350-355 (2008) - [j32]Koji Obata, Kazuyoshi Takagi, Naofumi Takagi:
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3772-3782 (2008) - [j31]Marcelo E. Kaihara, Naofumi Takagi:
Bipartite Modular Multiplication Method. IEEE Trans. Computers 57(2): 157-164 (2008) - [j30]Katsuki Kobayashi, Naofumi Takagi:
A Combined Circuit for Multiplication and Inversion in GF(2m). IEEE Trans. Circuits Syst. II Express Briefs 55-II(11): 1144-1148 (2008) - [c18]Nobutaka Kito, Naofumi Takagi:
Level-Testability of Multi-operand Adders. ATS 2008: 260-262 - [c17]Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. ISCAS 2008: 1688-1691 - 2007
- [j29]Koji Obata, Kazuyoshi Takagi, Naofumi Takagi:
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 257-266 (2007) - [j28]Koji Obata, Kazuyoshi Takagi, Naofumi Takagi:
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits. IEICE Trans. Electron. 90-C(12): 2278-2284 (2007) - [c16]Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi:
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2). IEEE Symposium on Computer Arithmetic 2007: 105-112 - 2006
- [j27]Fumio Kumazawa, Naofumi Takagi:
Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1799-1806 (2006) - [j26]Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division Using the SD2 Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(10): 2874-2881 (2006) - 2005
- [j25]Marcelo E. Kaihara, Naofumi Takagi:
A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3610-3617 (2005) - [j24]Marcelo E. Kaihara, Naofumi Takagi:
A Hardware Algorithm for Modular Multiplication/Division. IEEE Trans. Computers 54(1): 12-21 (2005) - [c15]Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi:
A Hardware Algorithm for Integer Division. IEEE Symposium on Computer Arithmetic 2005: 140-146 - [c14]Marcelo E. Kaihara, Naofumi Takagi:
Bipartite Modular Multiplication. CHES 2005: 201-210 - 2004
- [j23]Nhon T. Quach, Naofumi Takagi, Michael J. Flynn:
Systematic IEEE rounding method for high-speed floating-point multipliers. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 511-521 (2004) - 2003
- [j22]Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi:
Digit-Recurrence Algorithm for Computing Reciprocal Square-Root. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(1): 221-228 (2003) - [c13]Marcelo E. Kaihara, Naofumi Takagi:
A VLSI Algorithm for Modular Multiplication/Division. IEEE Symposium on Computer Arithmetic 2003: 220-227 - 2002
- [j21]Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi:
A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(5): 994-999 (2002) - [c12]Naofumi Takagi:
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms. ISMVL 2002: 224-237 - [c11]Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys:
Special Session: Security on SoC. ISSS 2002: 192-194 - 2001
- [j20]Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi:
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis. IEEE Trans. Computers 50(5): 394-398 (2001) - [c10]Naofumi Takagi:
A Hardware Algorithm for Computing Reciprocal Square Root. IEEE Symposium on Computer Arithmetic 2001: 94-100 - 2000
- [j19]Akira Higuchi, Naofumi Takagi:
A fast addition algorithm for elliptic curve arithmetic in GF(2n) using projective coordinates. Inf. Process. Lett. 76(3): 101-103 (2000) - [j18]Naofumi Takagi, Seiji Kuwahara:
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector. IEEE Trans. Computers 49(10): 1074-1082 (2000)
1990 – 1999
- 1999
- [j17]Naofumi Takagi, Takashi Horiyama:
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival. IEEE Trans. Computers 48(1): 76-80 (1999) - [c9]Naofumi Takagi, Seiji Kuwahara:
Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector. IEEE Symposium on Computer Arithmetic 1999: 86- - [r3]Naofumi Takagi, Charles R. Baugh, Saburo Muroga:
Multipliers. The VLSI Handbook 1999 - [r2]Naofumi Takagi, Saburo Muroga:
Dividers. The VLSI Handbook 1999 - [r1]Naofumi Takagi, Haruyuki Tago, Charles R. Baugh, Saburo Muroga:
Adders. The VLSI Handbook 1999 - 1998
- [j16]Naofumi Takagi:
Powering by a Table Look-Up and a Multiplication with Operand Modification. IEEE Trans. Computers 47(11): 1216-1222 (1998) - 1997
- [j15]Masayuki Ito, Naofumi Takagi, Shuzo Yajima:
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification. IEEE Trans. Computers 46(4): 495-498 (1997) - [j14]Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata:
O(n)-Depth Modular Exponentiation Circuit Algorithm. IEEE Trans. Computers 46(6): 701-704 (1997) - [c8]Naofumi Takagi:
Generating a Power of an Operand by a Table Look-up and a Multiplication. IEEE Symposium on Computer Arithmetic 1997: 126-131 - 1996
- [j13]Masayuki Ito, Naofumi Takagi, Shuzo Yajima:
Square Rooting by Iterative Multiply-Additions. Inf. Process. Lett. 60(5): 267-269 (1996) - 1995
- [j12]Naofumi Takagi:
A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions. IEICE Trans. Inf. Syst. 78-D(10): 1313-1315 (1995) - [c7]Masayuki Ito, Naofumi Takagi, Shuzo Yajima:
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root. IEEE Symposium on Computer Arithmetic 1995: 2-8 - [c6]Hannes Hassler, Naofumi Takagi:
Function Evaluation by Table Look-up and Addition. IEEE Symposium on Computer Arithmetic 1995: 10-16 - [c5]Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata:
O(n)-depth circuit algorithm for modular exponentiation. IEEE Symposium on Computer Arithmetic 1995: 188-192 - 1993
- [c4]Naofumi Takagi:
A modular multiplication algorithm with triangle additions. IEEE Symposium on Computer Arithmetic 1993: 272-276 - 1992
- [j11]Naofumi Takagi, Shuzo Yajima:
Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem. IEEE Trans. Computers 41(7): 887-891 (1992) - [j10]Naofumi Takagi:
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation. IEEE Trans. Computers 41(8): 949-956 (1992) - 1991
- [j9]Naofumi Takagi, Shuzo Yajima:
An on-line error-detectable high-speed array divider. Syst. Comput. Jpn. 22(1): 21-27 (1991) - [j8]Naofumi Takagi, Tohru Asada, Shuzo Yajima:
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation. IEEE Trans. Computers 40(9): 989-995 (1991) - [c3]Naofumi Takagi:
A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications. IEEE Symposium on Computer Arithmetic 1991: 35-42
1980 – 1989
- 1988
- [c2]Naofumi Takagi, Shuzo Yajima:
An on-line error-detectable array divider with a redundant binary representation and a residue code. FTCS 1988: 174-179 - 1987
- [j7]Naofumi Takagi, Tohru Asada, Shuzo Yajima:
A hardware algorithm for computing sine and cosine using redundant binary representation. Syst. Comput. Jpn. 18(8): 1-9 (1987) - [j6]Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima:
On high-speed parallel algorithms using redundant coding. Syst. Comput. Jpn. 18(12): 72-80 (1987) - [j5]Naofumi Takagi, Shuzo Yajima:
On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic. IEEE Trans. Computers 36(11): 1310-1317 (1987) - [c1]Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi:
Design of high speed MOS multiplier and divider using redundant binary representation. IEEE Symposium on Computer Arithmetic 1987: 80-86 - 1986
- [j4]Naofumi Takagi, Shuzo Yajima:
A square root hardware algorithm using redundant binary representation. Syst. Comput. Jpn. 17(11): 30-41 (1986) - [j3]Naofumi Takagi, Shuzo Yajima:
Hardware algorithms for computing exponentials and logarithms using redundant binary representation. Syst. Comput. Jpn. 17(12): 11-22 (1986) - 1985
- [j2]Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima:
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Trans. Computers 34(9): 789-796 (1985) - 1982
- [j1]Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima:
The Parallel Enumeration Sorting Scheme for VLSI. IEEE Trans. Computers 31(12): 1192-1201 (1982)
Coauthor Index
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