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"A 9-16Gb/s clock and data recovery circuit with three-state phase detector ..."

Afshin Rezayee, Kenneth Martin (2003)

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DOI: 10.1109/ESSCIRC.2003.1257227

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-04

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  dblp key:
  - conf/esscirc/RezayeeM03
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  - https://dblp.org/rec/conf/esscirc/RezayeeM03
Afshin Rezayee, Kenneth Martin:
A 9-16Gb/s clock and data recovery circuit with three-state phase detector and dual-path loop architecture. ESSCIRC 2003: 683-686

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