Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 23
Volume 23, Number 1, October 2017
- Zhaori Bi, Dian Zhou, Sheng-Guo Wang, Xuan Zeng:
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method. 1:1-1:25 - Jae Woong Jeong, Vishwanath Natarajan, Shreyas Sen, T. M. Mak, Jennifer Kitchen, Sule Ozev:
A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources. 2:1-2:21 - Korosh Vatanparvar, Mohammad Abdullah Al Faruque
:
Electric Vehicle Optimized Charge and Drive Management. 3:1-3:25 - Shuai Wang, Guangshan Duan, Yupeng Li, Qianhao Dong:
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime. 4:1-4:18 - Satya Trinadh Adireddy, Seetal Potluri, Ch. Sobhan Babu, Veezhinathan Kamakoti, Shiv Govind Singh:
Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing. 5:1-5:26 - Xingquan Li, Wenxing Zhu:
Two-Stage Layout Decomposition for Hybrid E-Beam and Triple Patterning Lithography. 6:1-6:23 - Sourav Das, Dongjin Lee, Wonje Choi, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs. 7:1-7:26 - Shanmugakumar Murugesan, Sk. Noor Mahammad:
A Novel Range Matching Architecture for Packet Classification Without Rule Expansion. 8:1-8:15 - P. R. Chithira, Vinita Vasudevan:
A Hierarchical Technique for Statistical Path Selection and Criticality Computation. 9:1-9:24 - Hyungon Moon, Jinyong Lee, Dongil Hwang, Seonhwa Jung, Jiwon Seo, Yunheung Paek:
Architectural Supports to Protect OS Kernels from Code-Injection Attacks and Their Applications. 10:1-10:25 - Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. 11:1-11:27 - Chao Chen, Giovanni Beltrame:
An Adaptive Markov Model for the Timing Analysis of Probabilistic Caches. 12:1-12:24
Volume 23, Number 2, January 2018
- Angeliki Kritikakou, Thibaut Marty, Matthieu Roy:
DYNASCORE: DYNAmic Software COntroller to Increase REsource Utilization in Mixed-Critical Systems. 13:1-13:26 - Jalil Boukhobza, Stéphane Rubini, Renhai Chen, Zili Shao:
Emerging NVM: A Survey on Architectural Integration and Research Challenges. 14:1-14:32 - Congming Gao, Liang Shi, Yejia Di, Qiao Li, Chun Jason Xue, Kaijie Wu, Edwin Hsing-Mean Sha:
Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs. 15:1-15:29 - Jaeyung Jun, Kyu Hyun Choi, Hokwon Kim, Sang Ho Yu, Seon Wook Kim, Youngsun Han:
Recovering from Biased Distribution of Faulty Cells in Memory by Reorganizing Replacement Regions through Universal Hashing. 16:1-16:21 - Hongxia Zhou, Chiu-Wing Sham, Hailong Yao:
Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits. 17:1-17:17 - Shao-Chung Wang, Li-Chen Kan, Chao-Lin Lee, Yuan-Shin Hwang, Jenq-Kuen Lee:
Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files. 18:1-18:25 - Leonardo Pereira Santos, Gabriel Luca Nazar, Luigi Carro:
Repair of FPGA-Based Real-Time Systems With Variable Slacks. 19:1-19:20 - Chen-Hsuan Lin, Lu Wan, Deming Chen:
C-Mine: Data Mining of Logic Common Cases for Improved Timing Error Resilience with Energy Efficiency. 20:1-20:23 - Kathrin Rosvall, Ingo Sander:
Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms. 21:1-21:26 - Johann Knechtel, Jens Lienig, Ibrahim Abe M. Elfadel:
Multi-Objective 3D Floorplanning with Integrated Voltage Assignment. 22:1-22:27 - Kun Yang, Hao-Ting Shen, Domenic Forte, Swarup Bhunia, Mark M. Tehranipoor:
Hardware-Enabled Pharmaceutical Supply Chain Security. 23:1-23:26 - Michail Noltsis, Dimitrios Rodopoulos, Nikolaos Zompakis, Francky Catthoor, Dimitrios Soudris:
Runtime Slack Creation for Processor Performance Variability using System Scenarios. 24:1-24:23 - Maryam Shafiee, Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Bertan Bakkaloglu, Sule Ozev:
A Disturbance-Free Built-In Self-Test and Diagnosis Technique for DC-DC Converters. 25:1-25:22 - Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros:
Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. 26:1-26:24
Volume 23, Number 3, April 2018
- Andres F. Gomez, Víctor H. Champac:
Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects. 27:1-27:21 - Sheng-Min Huang, Li-Pin Chang:
Providing SLO Compliance on NVMe SSDs Through Parallelism Reservation. 28:1-28:26 - Kun Yang, Domenic Forte, Mark M. Tehranipoor:
ReSC: An RFID-Enabled Solution for Defending IoT Supply Chain. 29:1-29:27 - Dongwook Lee, Andreas Gerstlauer:
Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs. 30:1-30:25 - Mahmood Naderan-Tahan, Hamid Sarbazi-Azad:
Domino Cache: An Energy-Efficient Data Cache for Modern Applications. 31:1-31:23 - Sheis Abolma'ali, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space. 32:1-32:25 - Majid Jalili, Hamid Sarbazi-Azad:
Express Read in MLC Phase Change Memories. 33:1-33:24 - Jin-Tai Yan:
Direction-Constrained Rectangle Escape Routing. 34:1-34:19 - Shengcheng Wang, Ran Wang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling. 35:1-35:25 - Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng:
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. 36:1-36:23 - Guan-Ruei Lu, Chun-Hao Kuo, Kuen-Cheng Chiang, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic Biochips. 37:1-37:25 - Mimi Xie, Chen Pan, Mengying Zhao, Yongpan Liu, Chun Jason Xue, Jingtong Hu:
Avoiding Data Inconsistency in Energy Harvesting Powered Embedded Systems. 38:1-38:25 - Luis Fernando Arcaro, Karila Palma Silva, Rômulo Silva de Oliveira:
On the Reliability and Tightness of GP and Exponential Models for Probabilistic WCET Estimation. 39:1-39:27 - Munish Jassi, Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs. 40:1-40:26
Volume 23, Number 4, July 2018
- Chris Chu, Mustafa Ozdal:
Introduction to the Special Section on Advances in Physical Design Automation. 41:1-41:2 - Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan:
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine. 42:1-42:23 - Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, David T. Westwick, Laleh Behjat:
Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints. 43:1-43:25 - Chen Wang, Yanan Sun, Shiyan Hu, Li Jiang, Weikang Qian:
Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit. 44:1-44:27 - Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin:
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. 45:1-45:26 - Fengxian Jiao, Sheqin Dong:
Ordered Escape Routing with Consideration of Differential Pair and Blockage. 46:1-46:26 - Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake:
Routable and Matched Layout Styles for Analog Module Generation. 47:1-47:17 - Pei-Yu Lee, Iris Hui-Ru Jiang:
iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis. 48:1-48:21 - Sayed Abdullah Sadat, Mustafa S. Canbolat, Selçuk Köse:
Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid. 49:1-49:15 - Burçin Çakir, Sharad Malik:
Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs. 50:1-50:19
- Philipp Ittershagen, Kim Grüttner, Wolfgang Nebel:
An Integration Flow for Mixed-Critical Embedded Systems on a Flexible Time-Triggered Platform. 51:1-51:25 - Yung-Chih Chen:
Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption. 52:1-52:25 - Irith Pomeranz:
Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests. 53:1-53:18 - Hengyang Zhao, Qi Hua, Hai-Bao Chen, Yaoyao Ye, Hai Wang, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle:
Thermal-Sensor-Based Occupancy Detection for Smart Buildings Using Machine-Learning Methods. 54:1-54:21 - Shalu, Srijan Kumar, Ananya Singla, Sudip Roy, Krishnendu Chakrabarty, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya:
Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips. 55:1-55:26
Volume 23, Number 5, October 2018
- Hantao Huang, Hang Xu, Yuehua Cai, Suleman Khalid Rai, Hao Yu:
Distributed Machine Learning on Smart-Gateway Network toward Real-Time Smart-Grid Energy Management with Behavior Cognition. 56:1-56:26 - Davide Zoni, Alessandro Barenghi, Gerardo Pelosi, William Fornaciari:
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture. 57:1-57:30 - Minjun Seo, Roman Lysecky:
Non-Intrusive In-Situ Requirements Monitoring of Embedded System. 58:1-58:27 - Irith Pomeranz:
Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences. 59:1-59:16 - Dongjin Lee, Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip. 60:1-60:25 - Inhak Han, Youngsoo Shin:
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. 61:1-61:21 - Eman M. Elmandouh, Amr G. Wassal:
Guiding Formal Verification Orchestration Using Machine Learning Methods. 62:1-62:33 - Keerthi K., Chester Rebeiro, Aritra Hazra:
An Algorithmic Approach to Formally Verify an ECC Library. 63:1-63:26 - Tseng-Yi Chen, Yuan-Hao Chang, Yuan-Hung Kuan, Ming-Chang Yang, Yu-Ming Chang, Pi-Cheng Hsiu:
Enhancing Flash Memory Reliability by Jointly Considering Write-back Pattern and Block Endurance. 64:1-64:24 - Guoqi Xie, Zhetao Li, Na Yuan, Renfa Li, Keqin Li:
Toward Effective Reliability Requirement Assurance for Automotive Functional Safety. 65:1-65:26 - Ziad Abuowaimer, Dani Maarouf, Timothy Martin, Jérémy Foxcroft, Gary Gréwal, Shawki Areibi, Anthony Vannelli:
GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures. 66:1-66:33 - Ramin Fallahzadeh, Hassan Ghasemzadeh:
Trading Off Power Consumption and Prediction Performance in Wearable Motion Sensors: An Optimal and Real-Time Approach. 67:1-67:23
Volume 23, Number 6, December 2018
- Siad Daboul, Stephan Held, Jens Vygen, Sonja Wittke:
An Approximation Algorithm for Threshold Voltage Optimization. 68:1-68:16 - Lorenzo Delledonne, Vittorio Zaccaria, Ruggero Susella, Guido Bertoni, Filippo Melzani:
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks. 69:1-69:17 - Doohwang Chang, Ganapati Bhat, Ümit Y. Ogras, Bertan Bakkaloglu, Sule Ozev:
Detection Mechanisms for Unauthorized Wireless Transmissions. 70:1-70:21 - Xuan Dong, Lihong Zhang:
PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction. 71:1-71:19 - Fatemeh Eslami, Steven J. E. Wilton:
Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug. 72:1-72:25 - Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing. 73:1-73:23
- Rasit Onur Topaloglu, Farinaz Koushanfar:
Editorial for TODAES Special Issue on Internet of Things System Performance, Reliability, and Security. - Kun Yang, Ulbert Botero, Hao-Ting Shen, Damon L. Woodard, Domenic Forte, Mark M. Tehranipoor:
UCR: An Unclonable Environmentally Sensitive Chipless RFID Tag For Protecting Supply Chain. 74:1-74:24 - Siam Umar Hussain, M. Sadegh Riazi, Farinaz Koushanfar:
SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFs. 75:1-75:20 - Ted Winograd, Gaurav Shenoy, Hassan Salmani, Hamid Mahmoodi, Setareh Rafatirad, Houman Homayoun:
Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering. 76:1-76:21 - Anh Truong, S. Rasoul Etesami, Negar Kiyavash:
Learning From Sleeping Experts: Rewarding Informative, Available, and Accurate Experts. 77:1-77:18 - Abhimanyu Chopra, Hakan Aydin, Setareh Rafatirad, Houman Homayoun:
Optimal Allocation of Computation and Communication in an IoT Network. 78:1-78:22 - Siam Umar Hussain, Farinaz Koushanfar:
P3: Privacy Preserving Positioning for Smart Automotive Systems. 79:1-79:19 - Md Muztoba, Rohit Voleti, Fatih Karabacak, Jaehyun Park, Ümit Y. Ogras:
Instinctive Assistive Indoor Navigation using Distributed Intelligence. 80:1-80:21 - Fatih Karabacak, Ümit Y. Ogras, Sule Ozev:
Remote Detection of Unauthorized Activity via Spectral Analysis. 81:1-81:21
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-26 18:26 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
