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ORCIDGong Chen 0002
Person information
- affiliation: Chengdu University of Information Technology, College of Communication Engineering, Chengdu, China
- affiliation (PhD 2015): University of Kitakyushu, Kitakyushu, Japan
Other persons with the same name
- Gong Chen — disambiguation page
- Gong Chen 0001 — MileBot Robotics Co., Ltd, Shenzhen, China (and 1 more)
- Gong Chen 0003
![[0000-0003-0714-9927]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-0714-9927")
— University of Science and Technology of China, School of Microelectronics, Hefei, China (and 1 more) - Gong Chen 0004 — Nanjing University of Aeronautics and Astronautics, College of Computer Science and Technology, Collaborative Innovation Center of Novel Software Technology and Industrialization, Nanjing, China (and 1 more)
- Gong Chen 0005 — Nanjing University of Posts and Telecommunications, College of Automation & College of Artificial Intelligence, Nanjing, China
- Gong Chen 0006 — Hong Kong Polytechnic University, Shenzhen Research Institute, Shenzhen, China (and 1 more)
- Gong Chen 0007 — East China Jiaotong University, School of Information Engineering, Nanchang, China
- Gong Chen 0008 — Shanghai Jiao Tong University, School of Electronic Information and Electrical Engineering, Shanghai, China
- Gong Chen 0009 — Georgia Institute of Technology, School of Electrical and Computer Engineering, Atlanta, GA, USA
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2010 – 2019
- 2018
[j4]Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake:
Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Design Autom. Electr. Syst. 23(4): 47:1-47:17 (2018)- 2016
- [j3]Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang:
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. ACM Trans. Design Autom. Electr. Syst. 21(3): 45:1-45:21 (2016) - [c8]Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen:
Twin-row-style for MOS analog layout. ICECS 2016: 141-144 - [c7]Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang:
Routability of twisted common-centroid capacitor array under signal coupling constraints. MWSCAS 2016: 1-4 - [c6]Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen:
A multi-functional memory unit with PLA-based reconfigurable decoder. ReConFig 2016: 1-7 - 2015
- [j2]Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1442-1454 (2015) - 2013
- [j1]Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2487-2498 (2013) - [c5]Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake:
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. ACM Great Lakes Symposium on VLSI 2013: 315-316 - [c4]Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake:
A comparator energy model considering shallow trench isolation stress by geometric programming. ISQED 2013: 585-590 - [c3]Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. VLSI-SoC 2013: 156-161 - 2012
- [c2]Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue:
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. ISCAS 2012: 938-941 - [c1]Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake:
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. ISQED 2012: 656-662
Coauthor Index
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