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ORCIDHiroki Nakahara
中原 啓貴
Person information
- unicode name: 中原 啓貴
- affiliation: Tokyo Institute of Technology, Japan
- affiliation: Ehime University, Matsuyama, Japan
- affiliation: Kagoshima University, Japan
- affiliation (PhD 2007): Kyushu Institute of Technology, Department of Computer Science and Electronics, Fukuoka, Japan
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Journal Articles
- 2023
[j29]Zhiqiang Que
, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(1): 4:1-4:26 (2023)- 2022
- [j28]Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara:
Multilayer Perceptron Training Accelerator Using Systolic Array. IEICE Trans. Inf. Syst. 105-D(12): 2048-2056 (2022) - [j27]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk:
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 227-237 (2022) - 2021
- [j26]Hiroki Nakahara, Takayuki Tanaka, Ichihiko Toyoda:
A novel compact planar magic-T using CPS and microstrip-to-CPS transition. IEICE Electron. Express 18(15): 20210256 (2021) - [j25]Naoto Soga, Shimpei Sato, Hiroki Nakahara:
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. IEICE Trans. Inf. Syst. 104-D(8): 1121-1129 (2021) - [j24]Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. IEICE Trans. Inf. Syst. 104-D(12): 2040-2047 (2021) - [j23]Ryosuke Kuramochi, Hiroki Nakahara:
A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA. IEICE Trans. Inf. Syst. 104-D(12): 2068-2077 (2021) - [j22]Masayuki Shimoda, Youki Sada, Hiroki Nakahara:
FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. J. Signal Process. Syst. 93(5): 499-512 (2021) - 2020
- [j21]Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara:
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. 103-D(12): 2463-2470 (2020) - 2019
- [j20]Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato:
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. 102-D(5): 1003-1011 (2019) - [j19]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. 102-D(5): 1020-1028 (2019) - 2018
- [j18]Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design. IEICE Trans. Inf. Syst. 101-D(2): 354-362 (2018) - [j17]Tomoya Fujii, Shimpei Sato, Hiroki Nakahara:
A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. IEICE Trans. Inf. Syst. 101-D(2): 376-386 (2018) - [j16]Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - 2016
- [j15]Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura:
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 73-86 (2016) - [j14]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto:
An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k). J. Multiple Valued Log. Soft Comput. 26(1-2): 109-123 (2016) - [j13]Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao:
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. SIGARCH Comput. Archit. News 44(4): 44-49 (2016) - 2015
- [j12]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao:
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. IEICE Trans. Inf. Syst. 98-D(2): 262-271 (2015) - 2014
- [j11]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Packet Classifier Based on Prefetching EVMDD (k) Machines. IEICE Trans. Inf. Syst. 97-D(9): 2243-2252 (2014) - [j10]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. J. Multiple Valued Log. Soft Comput. 23(3-4): 365-377 (2014) - 2013
- [j9]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. IEICE Trans. Inf. Syst. 96-D(8): 1667-1675 (2013) - 2012
- [j8]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. IEICE Trans. Inf. Syst. 95-D(2): 364-373 (2012) - [j7]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. Microprocess. Microsystems 36(8): 644-664 (2012) - [j6]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. J. Multiple Valued Log. Soft Comput. 19(1-3): 203-217 (2012) - [j5]Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao:
On a wideband fast fourier transform for a radio telescope. SIGARCH Comput. Archit. News 40(5): 46-51 (2012) - 2010
- [j4]Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler:
A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Trans. Inf. Syst. 93-D(8): 2026-2035 (2010) - [j3]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. IEICE Trans. Inf. Syst. 93-D(8): 2048-2058 (2010) - 2006
- [j2]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3471-3481 (2006) - 2005
- [j1]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Design Algorithm for Sequential Circuits Using LUT Rings. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3342-3350 (2005)
Conference and Workshop Papers
- 2024
- [c77]Ryota Kayanoma, Hiroki Nakahara:
A Weight Ternary Ensemble Vision Transformer Toward Memory Size Reduction. ISMVL 2024: 155-160 - 2023
- [c76]Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara:
A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA. ARC 2023: 338-353 - [c75]Kennichi Nakamura, Hiroki Nakahara:
A Consideration on Ternary Adversarial Generative Networks. ISMVL 2023: 1-6 - [c74]Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara:
A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference. MCSoC 2023: 446-453 - 2022
- [c73]Wei Zhang, Ray C. C. Cheung, Yun Liang, Hiroki Nakahara:
Message from the General Chair and Program Co-Chairs. FPT 2022: 1 - [c72]Yun Liang, Hiroki Nakahara, Wei Zhang, Fubing Mao, Ray C. C. Cheung:
Preface. FPT 2022: i - [c71]Kennichi Nakamura, Hiroki Nakahara:
Optimizations of Ternary Generative Adversarial Networks. ISMVL 2022: 158-163 - [c70]Ryota Kayanoma, Hiroki Nakahara:
Fast Interface with Ensemble Ternary Neural Network. ISMVL 2022: 182-187 - 2021
- [c69]Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara:
A Multilayer Perceptron Training Accelerator using Systolic Array. APCCAS 2021: 77-80 - [c68]Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS 2021: 1-21 - [c67]Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara:
A High-Throughput Detection Circuit based on 2q+1-Valued Deep Neural Networks. ISMVL 2021: 142-147 - [c66]Pintusorn Suttiponpisarn, Chalermpol Charnsripinyo, Sasiporn Usanavasin, Hiroki Nakahara:
Detection of Wrong Direction Vehicles on Two-Way Traffic. KSE 2021: 1-6 - 2020
- [c65]Hiroki Nakahara, Zhiqiang Que, Wayne Luk:
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. FCCM 2020: 1-9 - [c64]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Optimizing Reconfigurable Recurrent Neural Networks. FCCM 2020: 10-18 - [c63]Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. FCCM 2020: 229 - [c62]Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk:
R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. FPGA 2020: 319 - [c61]Ryosuke Kuramochi, Hiroki Nakahara:
An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. FPL 2020: 298-303 - [c60]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT 2020: 20-28 - [c59]Naoto Soga, Hiroki Nakahara:
Design Method for an LUT Network-Based CNN with a Sparse Local Convolution. FPT 2020: 294-295 - [c58]Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops 2020: 143-146 - [c57]Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara:
A Table Look-Up Based Ternary Neural Network Processor. ISMVL 2020: 188-193 - [c56]Hiroki Nakahara:
2n+1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle. ISMVL 2020: 200-205 - 2019
- [c55]Masayuki Shimoda, Youki Sada, Hiroki Nakahara:
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. ARC 2019: 371-386 - [c54]Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato:
An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA 2019: 186 - [c53]Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato:
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL 2019: 180-186 - [c52]Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara:
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. FPL 2019: 413-414 - [c51]Akira Jinguji, Youki Sada, Hiroki Nakahara:
Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA. FPL 2019: 424-425 - [c50]Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara:
A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. FPT 2019: 267-270 - [c49]Atsuki Munakata, Hiroki Nakahara, Shimpei Sato:
Noise Convolutional Neural Networks and FPGA Implementation. ISMVL 2019: 85-90 - [c48]Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC 2019: 93-100 - [c47]Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara:
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig 2019: 1-5 - 2018
- [c46]Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato:
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA 2018: 31-40 - [c45]Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL 2018: 457-458 - [c44]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL 2018: 461-462 - [c43]Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT 2018: 298-301 - [c42]Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara:
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. FPT 2018: 310-313 - [c41]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART 2018: 10:1-10:6 - [c40]Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara:
A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). HEART 2018: 20:1-20:4 - [c39]Hiroki Nakahara, Tsutomu Sasao:
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. ISCAS 2018: 1-5 - [c38]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara:
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL 2018: 174-179 - [c37]Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura:
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. VLSI Circuits 2018: 41-42 - 2017
- [c36]Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura:
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. ARC 2017: 268-280 - [c35]Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura:
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA 2017: 290 - [c34]Hiroki Nakahara, Tomoya Fujii, Shimpei Sato:
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. FPL 2017: 1-4 - [c33]Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato:
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT 2017: 168-175 - [c32]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
All binarized convolutional neural network and its implementation on an FPGA. FPT 2017: 291-294 - [c31]Haruyoshi Yonekawa, Hiroki Nakahara:
On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. IPDPS Workshops 2017: 98-105 - [c30]Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao:
A Random Forest Using a Multi-valued Decision Diagram on an FPGA. ISMVL 2017: 266-271 - [c29]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119 - 2016
- [c28]Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura:
A memory-based realization of a binarized deep convolutional neural network. FPT 2016: 277-280 - [c27]Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato:
An acceleration of a random forest classification using Altera SDK for OpenCL. FPT 2016: 289-292 - [c26]Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa:
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope. ISMVL 2016: 60-65 - 2015
- [c25]Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao:
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. ARC 2015: 267-279 - [c24]Hiroki Nakahara, Tsutomu Sasao:
A deep convolutional neural network based on nested residue number system. FPL 2015: 1-6 - [c23]Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai:
An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD. ISMVL 2015: 97-102 - 2014
- [c22]Kenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto:
Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization. ISIC 2014: 584-587 - [c21]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). ISMVL 2014: 1-6 - [c20]Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai:
An AWF digital spectrometer for a radio telescope. ReConFig 2014: 1-6 - 2013
- [c19]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
An Architecture for IPv6 Lookup Using Parallel Index Generation Units. ARC 2013: 59-71 - [c18]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A packet classifier using LUT cascades based on EVMDDS (k). FPL 2013: 1-6 - [c17]Hiroki Nakahara, Kazumasa Iwai, Hiroyuki Nakanishi:
A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst. FPT 2013: 430-433 - [c16]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. ISMVL 2013: 90-95 - 2012
- [c15]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. ARC 2012: 202-214 - [c14]Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao:
On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. ICA3PP (1) 2012: 202-217 - [c13]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. ISMVL 2012: 148-153 - 2011
- [c12]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Regular Expression Matching Circuit Based on a Decomposed Automaton. ARC 2011: 16-28 - [c11]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. ISMVL 2011: 125-130 - 2010
- [c10]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Packet Classifier Using a Parallel Branching Program Machine. DSD 2010: 745-752 - [c9]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Comparison of Architectures for Various Decision Diagram Machines. ISMVL 2010: 229-234 - 2009
- [c8]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC 2009: 261-267 - [c7]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
The Parallel Sieve Method for a Virus Scanning Engine. DSD 2009: 809-816 - [c6]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
A virus scanning engine using a parallel finite-input memory machine and MPUs. FPL 2009: 635-639 - [c5]Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler:
A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL 2009: 362-369 - 2007
- [c4]Tsutomu Sasao, Hiroki Nakahara:
Implementations of Reconfigurable Logic Arrays on FPGAs. FPT 2007: 217-223 - [c3]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A CAM Emulator Using Look-Up Table Cascades. IPDPS 2007: 1-8 - 2006
- [c2]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A fast logic simulator using a look up table cascade emulator. ASP-DAC 2006: 466-472 - [c1]Hiroki Nakahara, Tsutomu Sasao:
A Soft Error Tolerant LUT Cascade Emulator. ATS 2006: 115-124
Parts in Books or Collections
- 2018
- [p1]Kentaro Sano, Hiroki Nakahara:
Hardware Algorithms. Principles and Structures of FPGAs 2018: 137-177
Coauthor Index
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