"A High-speed Low-power Deep Neural Network on an FPGA based on the Nested ..."

Hiroki Nakahara, Tsutomu Sasao (2018)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2018.8351850

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/NakaharaS18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/NakaharaS18
Hiroki Nakahara, Tsutomu Sasao:
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. ISCAS 2018: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.