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ORCID11. ARC 2015: Bochum, Germany
- Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz:
Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings. Lecture Notes in Computer Science 9040, Springer 2015, ISBN 978-3-319-16213-3
Architecture and Modeling
- Thiago Baldissera Biazus, Mateus Beck Rutzig
:
Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks. 3-14 - Yaman Umuroglu, Magnus Jahre:
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators. 15-26 - Rehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas:
Hierarchical Dynamic Power-Gating in FPGAs. 27-38
Tools and Compilers I
- Ian Graves, Adam M. Procter, William L. Harrison, Michela Becchi, Gerard Allwein:
Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation. 41-52 - Shimpei Sato, Kenji Kise:
ArchHDL: A Novel Hardware RTL Design Environment in C++. 53-64 - Zaid Al-Khatib, Samar Abdi:
Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA. 65-76
Systems and Applications I
- Markus Happe, Andreas Traber, Ariane Keller:
Preemptive Hardware Multitasking in ReconOS. 79-90 - Fynn Schwiegelshohn, Eugen Ossovski, Michael Hübner:
A Fully Parallel Particle Filter Architecture for FPGAs. 91-102 - Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker:
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. 103-114
Tools and Compilers II
- Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris:
Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures. 117-128 - Luca Sterpone, Boyang Du:
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs. 129-140 - Philipp A. Hartmann, Kim Grüttner, Wolfgang Nebel:
Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties. 141-152 - Xerach Peña, Fernando Rincón, Julio Dondo, Julián Caba, Juan Carlos López:
Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components. 153-164
Network-on-a-Chip
- Michael Metzner, Jesus Lizarraga, Christophe Bobda:
Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays. 167-178 - Philipp Gorski, Tim Wegner, Dirk Timmermann:
Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip. 179-190 - Salma Hesham, Jens Rettkowski, Diana Göhringer, Mohamed A. Abd El Ghany:
Survey on Real-Time Network-on-Chip Architectures. 191-202
Cryptography Applications
- Bilal Habib, Jens-Peter Kaps, Kris Gaj:
Efficient SR-Latch PUF. 205-216 - Ekawat Homsirikamol, Kris Gaj:
Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study. 217-228 - João Carlos Resende, Ricardo Chaves:
Dual CLEFIA/AES Cipher Core on FPGA. 229-240
Systems and Applications II
- Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink:
An Efficient and Flexible FPGA Implementation of a Face Detection System. 243-254 - Jens Rettkowski, Philipp Wehner, Marc Schülper, Diana Göhringer:
A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context. 255-266 - Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao:
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. 267-279 - Tobias Strauch:
The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs. 280-290
Extended Abstracts (Posters)
- Anupam Chattopadhyay, Xiaolin Chen:
A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures. 293-300 - Zoltán Endre Rákossy, Dominik Stengele, Axel Acosta-Aponte, Saumitra Chafekar, Paolo Bientinesi, Anupam Chattopadhyay:
Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. 301-310 - Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker:
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. 311-320 - Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos:
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures. 321-330 - Lucas A. Tambara, Felipe Almeida, Paolo Rech, Fernanda Lima Kastensmidt, Giovanni Bruni, Christopher Frost:
Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects. 331-338 - Paulo Matias, Rafael Tuma Guariento, Lírio Onofre Baptista de Almeida, Jan Frans Willem Slaets:
Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments. 339-348 - Ren Chen, Viktor K. Prasanna:
DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems. 349-356 - Pavlos Giakoumakis, Grigorios Chrysos, Apostolos Dollas, Ioannis Papaefstathiou:
Acceleration of Data Streaming Classification using Reconfigurable Technology. 357-364 - Tobias Wiersema, Sen Wu, Marco Platzner:
On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach. 365-372 - Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul:
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. 373-382 - Takuma Usui, Ryohei Kobayashi, Kenji Kise:
A Challenge of Portable and High-Speed FPGA Accelerator. 383-392 - Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara:
Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array. 393-400 - Stephan Nolting, Guillermo Payá-Vayá, Florian Giesemann, Holger Blume:
Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture. 401-410 - Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid:
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. 411-418 - Ernesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Jiang Chau Wang:
DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost. 419-426 - Zeyad Aklah, David Andrews:
A Flexible Multilayer Perceptron Co-processor for FPGAs. 427-434 - Maikon Adiles Fernandez Bueno, Carlos R. P. Almeida Jr., José A. M. de Holanda, Eduardo Marques:
Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs. 435-442 - Shreyas G. Singapura, Anand V. Panangadan, Viktor K. Prasanna:
Towards Performance Modeling of 3D Memory Integrated FPGA Architectures. 443-450 - Shinya Takamaeda-Yamazaki:
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. 451-460
Special Session 1: Funded R&D Running and Completed Projects (Invited Papers)
- Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato:
Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing. 463-474 - George Lentaris, Ioannis Stamoulias, Dionysios Diamantopoulos, Konstantinos Maragos, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez, Manolis I. A. Lourakis, Xenophon Zabulis, Ioannis Kostavelis, Lazaros Nalpantidis, Evangelos Boukas, Antonios Gasteratos:
SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms. 475-486 - George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, Dionisios N. Pnevmatikatos:
Hardware Task Scheduling for Partially Reconfigurable FPGAs. 487-498 - Vasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris, Leonidas Lymperopoulos:
SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring. 499-510
Special Session 2: Horizon 2020 Funded Projects (Invited Papers)
- Nele Mentens, Jochen Vandorpe, Jo Vliegen, An Braeken, Bruno da Silva, Abdellah Touhafi, Alois Kern, Stephan Knappmann, Jens Rettkowski, Muhammed Al Kadi, Diana Göhringer, Michael Hübner:
DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications. 513-518 - Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner, Diana Göhringer, Maria Dagioglou, Theodoros Giannakopoulos, Stasinos Konstantopoulos, Vangelis Karkaletsis:
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective. 519-530 - Andreas Raptopoulos, Sotirios Xydis, Dimitrios Soudris:
Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach. 531-541 - Ioannis Papaefstathiou, Gregory Chrysos, Lambros Sarakis:
COSSIM: A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator. 542-553
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