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Journal Articles

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2016
[j18]
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Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, Jean-François Naviner:
Efficient reliability evaluation methodologies for combinational circuits. Microelectron. Reliab. 64: 19-25 (2016)
2015
[j17]
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Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit, Jean-François Naviner:
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects. Microelectron. Reliab. 55(3-4): 645-653 (2015)
2013
[j16]
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Samuel N. Pagliarini, Arwa Ben Dhia, Lirida Alves de Barros Naviner, Jean-François Naviner:
SNaP: A novel hybrid method for circuit reliability assessment under multiple faults. Microelectron. Reliab. 53(9-11): 1230-1234 (2013)
2012
[j15]
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Hao Cai, Hervé Petit, Jean-François Naviner:
A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems. J. Low Power Electron. 8(5): 697-705 (2012)
[j14]
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Samuel N. Pagliarini, G. G. dos Santos, Lirida Alves de Barros Naviner, Jean-François Naviner:
Exploring the feasibility of selective hardening for combinational logic. Microelectron. Reliab. 52(9-10): 1843-1847 (2012)
2011
[j13]
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Pietro Maris Ferreira, Hervé Petit, Jean-François Naviner:
A synthesis methodology for AMS/RF circuit reliability: Application to a DCO design. Microelectron. Reliab. 51(4): 765-772 (2011)
[j12]
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Hao Cai, Hervé Petit, Jean-François Naviner:
Reliability aware design of low power continuous-time sigma-delta modulator. Microelectron. Reliab. 51(9-11): 1449-1453 (2011)
[j11]
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Lirida A. B. Naviner, Jean-François Naviner, G. G. dos Santos Jr., Elaine Crespo Marques, Nilson M. Paiva Jr.:
FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level. Microelectron. Reliab. 51(9-11): 1459-1463 (2011)
2010
[j10]
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G. G. dos Santos, Elaine Crespo Marques, Lirida A. B. Naviner, Jean-François Naviner:
Using error tolerance of target application for efficient reliability improvement of digital circuits. Microelectron. Reliab. 50(9-11): 1219-1222 (2010)
[j9]
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Elaine Crespo Marques, Lirida A. B. Naviner, Jean-François Naviner:
An efficient tool for reliability improvement based on TMR. Microelectron. Reliab. 50(9-11): 1247-1250 (2010)
2008
[j8]
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Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner, Jean-François Naviner:
Signal probability for reliability evaluation of logic circuits. Microelectron. Reliab. 48(8-9): 1586-1591 (2008)
[j7]
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Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner, Jean-François Naviner:
Relevant metrics for evaluation of concurrent error detection schemes. Microelectron. Reliab. 48(8-9): 1601-1603 (2008)
[j6]
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David Camarero, Karim Ben Kalaia, Jean-François Naviner, Patrick Loumeau:
Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3676-3687 (2008)
2006
[j5]
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Denis Teixeira Franco, Jean-François Naviner, Lirida A. B. Naviner:
Yield and reliability issues in nanoelectronic technologies. Ann. des Télécommunications 61(11-12): 1422-1457 (2006)
2004
[j4]
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Jean-François Naviner, Amara Amara:
Systems-on-chip for telecommunications. Ann. des Télécommunications 59(7-8): 755-758 (2004)
2003
[j3]
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  - journals/tim/CatundaNDF03
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Sebastian Yuri Cavalcanti Catunda, Jean-François Naviner, Gurdip Singh Deep, Raimundo Carlos Silvério Freire:
Designing a programmable analog signal conditioning circuit without loss of measurement range. IEEE Trans. Instrum. Meas. 52(5): 1482-1487 (2003)
2002
[j2]
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Patrick Loumeau, Jean-François Naviner, Hervé Petit, Lirida A. B. Naviner, Patricia Desgreys:
Analog to digital conversion: technical aspects. Ann. des Télécommunications 57(5-6): 338-385 (2002)
1993
[j1]
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Jean-François Naviner, Jean-Claude Dufourd:
Préforme/aGAPE: a synergy between symbolic cell design and assembly. Microprocess. Microprogramming 37(1-5): 11-14 (1993)

Conference and Workshop Papers

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2014
[c32]
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Lirida A. B. Naviner, Kaikai Liu, Hao Cai, Jean-François Naviner:
Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. ICICDT 2014: 1-4
[c31]
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Samuel N. Pagliarini, Lirida A. B. Naviner, Jean-François Naviner, Dhiraj K. Pradhan:
A hybrid reliability assessment method and its support of sequential logic modelling. IOLTS 2014: 182-183
2013
[c30]
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Kaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit:
Reliability analysis of combinational circuits with the influences of noise and single-event transients. DFTS 2013: 218-223
[c29]
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Kaikai Liu, Ting An, Hao Cai, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit:
A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. EUROCON 2013: 1829-1836
[c28]
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Samuel N. Pagliarini, Lirida A. B. Naviner, Jean-François Naviner:
Single event transient mitigation through pulse quenching: Effectiveness at circuit level. ICECS 2013: 121-124
[c27]
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Samuel N. Pagliarini, Tian Ban, Lirida A. B. Naviner, Jean-François Naviner:
Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. MWSCAS 2013: 113-116
[c26]
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Hao Cai, Hervé Petit, Jean-François Naviner:
A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts. NEWCAS 2013: 1-4
[c25]
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Samuel N. Pagliarini, Lirida A. B. Naviner, Jean-François Naviner:
Selective hardening against multiple faults employing a net-based reliability analysis. NEWCAS 2013: 1-4
2012
[c24]
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Samuel N. Pagliarini, Arwa Ben Dhia, Lirida Alves de Barros Naviner, Jean-François Naviner:
Automatic selective hardening against soft errors: A cost-based and regularity-aware approach. ICECS 2012: 753-756
[c23]
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Samuel Nascimento Pagliarini, Lirida A. B. Naviner, Jean-François Naviner:
Selective hardening methodology for combinational logic. LATW 2012: 1-6
[c22]
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Kaikai Liu, Tian Ban, Lirida A. B. Naviner, Jean-François Naviner:
Reliability analysis of a Reed-Solomon decoder. MWSCAS 2012: 438-441
2011
[c21]
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  - conf/iscas/FerreiraPN11
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Pietro Maris Ferreira, Hervé Petit, Jean-François Naviner:
A new synthesis methodology for reliable RF front-end Design. ISCAS 2011: 2926-2929
2010
[c20]
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Pietro Maris Ferreira, Hervé Petit, Jean-François Naviner:
AMS and RF design for reliability methodology. ISCAS 2010: 3657-3660
[c19]
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  - conf/sbcci/FrancoVNN10
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Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner, Jean-François Naviner:
On evaluating the signal reliability of self-checking arithmetic circuits. SBCCI 2010: 109-114
2008
[c18]
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Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner, Jean-François Naviner:
Reliability analysis of logic circuits based on signal probability. ICECS 2008: 670-673
[c17]
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  - conf/icecsys/VasconcelosFNN08
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Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner, Jean-François Naviner:
On the output events in concurrent error detection schemes. ICECS 2008: 978-981
[c16]
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  - conf/imtic/RiazNN08
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Aamir Riaz, Jean-François Naviner, Van Tam Nguyen:
A Novel Approach to Non Coherent UWB Reception. IMTIC 2008: 100-109
2006
[c15]
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  - conf/icecsys/MinaGN06
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Rayan Mina, Jean-Charles Grasset, Jean-François Naviner:
Impact of charge injection on system-level performance of a discrete-time GSM receiver. ICECS 2006: 494-497
[c14]
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  - conf/iscas/NguyenLN06
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Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
High-pass Delta Sigma modulator: from system analysis to circuit design. ISCAS 2006
[c13]
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Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
A CMOS implementation of time-interleaved high-pass Delta Sigma modulator. ISCAS 2006
2005
[c12]
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  - conf/icecsys/CamareroNL05
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David Camarero, Jean-François Naviner, Patrick Loumeau:
Calibration of sampling instants in a multiple channel time-interleaved analog-to-digital converter. ICECS 2005: 1-4
2004
[c11]
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David Camarero, Jean-François Naviner, Patrick Loumeau:
Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters. SBCCI 2004: 228-232
2003
[c10]
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  - conf/icassp/NguyenLN03
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Van-Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
Temporel and spectral analysis of time interleaved high pass sigma delta converter. ICASSP (2) 2003: 453-456
2002
[c9]
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Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
An interleaved delta-sigma analog to digital converter with digital correction. ICASSP 2002: 4193
[c8]
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Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
A time-interleaved chopper-stabilized delta-sigma analog to digital converter. ICECS 2002: 299-302
[c7]
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Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
Analysis of time-interleaved delta-sigma analog to digital converter. VTC Spring 2002: 1594-1597
2001
[c6]
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  - conf/icecsys/ColinLNN01
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Elizabeth Colin, Patrick Loumeau, Lirida A. B. Naviner, Jean-François Naviner:
Antialiasing filtering influences on ADC specifications for radio receivers. ICECS 2001: 1469-1472
[c5]
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  - conf/iscas/MendesLN01
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Elizabeth de Lira Mendes, Patrick Loumeau, Jean-François Naviner:
A switched-current sample and hold circuit for low frequency applications. ISCAS (1) 2001: 452-455
[c4]
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Elizabeth Colin, Lirida A. B. Naviner, Patrick Loumeau, Jean-François Naviner:
Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers. VTC Fall 2001: 2351-2354
1999
[c3]
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  - conf/iscas/VasseauxHLN99
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T. Vasseaux, B. Huyart, Patrick Loumeau, Jean-François Naviner:
A track&hold-mixer for direct-conversion by subsampling. ISCAS (4) 1999: 584-587
1994
[c2]
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  - conf/eurodac/DufourN94
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Jean-Claude Dufourd, Jean-François Naviner:
An Optimizable Model for Process Independent Symbolic Design. EDAC-ETC-EUROASIC 1994: 660
1990
[c1]
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Jean-Claude Dufourd, Jean-François Naviner, Francis Jutand:
Preform: A Process Independent Symbolic Layout System. ICCAD 1990: 248-251

Informal and Other Publications

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2008
[i1]
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Lirida Alves de Barros Naviner, Jean-François Naviner, Denis Teixeira Franco, Maí Correia R. de Vasconcelos:
Methods and Metrics for Reliability Assessment. Fault-Tolerant Distributed Algorithms on VLSI Chips 2008

Coauthor Index

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